公开(公告)号：US10361112B2

公开(公告)日：2019-07-23

申请号：US15725996

申请日：2017-10-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Lin Tsai ,  Shing-Chyang Pan ,  Sung-En Lin ,  Tze-Liang Lee ,  Jung-Hau Shiu ,  Jen Hung Wang

IPC: H01L29/66 ,  H01L29/49 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/768 ,  H01L21/762 ,  H01L21/02

Abstract: The present disclosure describes a method of forming a dielectric layer or a dielectric stack on a photoresist layer while minimizing or avoiding damage to the photoresist. In addition, the dielectric layer or dielectric stack can till high-aspect ratio openings and can be removed with etching. The dielectric layer or dielectric stack can be deposited with a conformal, low-temperature chemical vapor deposition process or a conformal, low-temperature atomic layer deposition process that utilizes a number of precursors and plasmas or reactant gases.

公开(公告)号：US20240282571A1

公开(公告)日：2024-08-22

申请号：US18639575

申请日：2024-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Lin Tsai ,  Jung-Hau Shiu ,  Ching-Yu Chang ,  Jen Hung Wang ,  Shing-Chyang Pan ,  Tze-Liang Lee

IPC: H01L21/02 ,  C23C14/06 ,  C23C14/08 ,  C23C14/22 ,  C23C16/02 ,  C23C16/04 ,  C23C16/30 ,  C23C16/40 ,  C23C16/455 ,  H01J37/32 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/66

CPC classification number: H01L21/02126 ,  C23C14/0676 ,  C23C14/08 ,  C23C16/0245 ,  C23C16/042 ,  C23C16/045 ,  C23C16/308 ,  C23C16/401 ,  C23C16/45529 ,  C23C16/45536 ,  C23C16/45553 ,  H01L21/0214 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/823821 ,  H01L29/66795 ,  C23C14/228 ,  H01J37/32082 ,  H01J37/32174 ,  H01L21/76808 ,  H01L23/528

Abstract: A method of manufacturing a semiconductor device includes depositing a dielectric layer over a substrate, performing a first patterning to form an opening in the dielectric layer, and depositing an oxide film over and contacting the dielectric layer and within the opening in the dielectric layer. The oxide film is formed from multiple precursors that are free of O2, and depositing the oxide film includes forming a plasma of a first precursor of the multiple precursors.

公开(公告)号：US20210134656A1

公开(公告)日：2021-05-06

申请号：US17119692

申请日：2020-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ren Wang ,  Shing-Chyang Pan ,  Ching-Yu Chang ,  Wan-Lin Tsai ,  Jung-Hau Shiu ,  Tze-Liang Lee

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L21/033

Abstract: Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over an underlying layer, patterning the first mask layer to form a first opening, forming a non-conformal film over the first mask layer, wherein a first thickness of the non-conformal film formed on the top surface of the first mask layer is greater than a second thickness of the non-conformal film formed on a sidewall surface of the first mask layer, performing a descum process, wherein the descum process removes a portion of the non-conformal film within the first opening, and etching the underlying layer using the patterned first mask layer and remaining portions of the non-conformal film as an etching mask.

公开(公告)号：US11676852B2

公开(公告)日：2023-06-13

申请号：US17119692

申请日：2020-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ren Wang ,  Shing-Chyang Pan ,  Ching-Yu Chang ,  Wan-Lin Tsai ,  Jung-Hau Shiu ,  Tze-Liang Lee

IPC: H01L21/76 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L21/033

CPC classification number: H01L21/76802 ,  H01L21/0228 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76879

Abstract: Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over an underlying layer, patterning the first mask layer to form a first opening, forming a non-conformal film over the first mask layer, wherein a first thickness of the non-conformal film formed on the top surface of the first mask layer is greater than a second thickness of the non-conformal film formed on a sidewall surface of the first mask layer, performing a descum process, wherein the descum process removes a portion of the non-conformal film within the first opening, and etching the underlying layer using the patterned first mask layer and remaining portions of the non-conformal film as an etching mask.

公开(公告)号：US12074058B2

公开(公告)日：2024-08-27

申请号：US18308937

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ren Wang ,  Shing-Chyang Pan ,  Ching-Yu Chang ,  Wan-Lin Tsai ,  Jung-Hau Shiu ,  Tze-Liang Lee

IPC: H01L21/76 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76879

Abstract: Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over an underlying layer, patterning the first mask layer to form a first opening, forming a non-conformal film over the first mask layer, wherein a first thickness of the non-conformal film formed on the top surface of the first mask layer is greater than a second thickness of the non-conformal film formed on a sidewall surface of the first mask layer, performing a descum process, wherein the descum process removes a portion of the non-conformal film within the first opening, and etching the underlying layer using the patterned first mask layer and remaining portions of the non-conformal film as an etching mask.

公开(公告)号：US20230420452A1

公开(公告)日：2023-12-28

申请号：US17848605

申请日：2022-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Qiang Wen ,  Shih-Fen Huang ,  Shih-Chun Fu ,  Chi-Yuan Shih ,  Feng Yuan ,  Wan-Lin Tsai ,  Chung-Liang Cheng

IPC: H01L27/06 ,  H01L29/8605 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/0629 ,  H01L29/8605 ,  H01L29/7851 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66166

Abstract: Embodiments include a FinFET transistor including an embedded resistor disposed in the fin between the source epitaxial region and the source contact. A control contact may be used to bias the embedded resistor, thereby changing the resistivity of the resistor. Edge gates of the FinFET transistor may be replaced with insulating structures. Multiple ones of the FinFET/embedded resistor combination may be utilized together in a common drain/common source contact design.

公开(公告)号：US20230260829A1

公开(公告)日：2023-08-17

申请号：US18308937

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ren Wang ,  Shing-Chyang Pan ,  Ching-Yu Chang ,  Wan-Lin Tsai ,  Jung-Hau Shiu ,  Tze-Liang Lee

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L21/033

CPC classification number: H01L21/76802 ,  H01L21/76879 ,  H01L21/31144 ,  H01L21/02167 ,  H01L21/0228 ,  H01L21/02274 ,  H01L21/02211 ,  H01L21/0337

Abstract: Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over an underlying layer, patterning the first mask layer to form a first opening, forming a non-conformal film over the first mask layer, wherein a first thickness of the non-conformal film formed on the top surface of the first mask layer is greater than a second thickness of the non-conformal film formed on a sidewall surface of the first mask layer, performing a descum process, wherein the descum process removes a portion of the non-conformal film within the first opening, and etching the underlying layer using the patterned first mask layer and remaining portions of the non-conformal film as an etching mask.