公开(公告)号：US20190164751A1

公开(公告)日：2019-05-30

申请号：US15880389

申请日：2018-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chien CHI ,  Hsiao-Kuan WEI ,  Hung-Wen SU ,  Pei-Hsuan LEE ,  Hsin-Yun HSU ,  Jui-Fen CHIEN

IPC: H01L21/02 ,  H01L21/28 ,  H01L27/092 ,  H01L21/20 ,  H01L21/324 ,  H01L29/423 ,  H01L29/49 ,  H01L21/762 ,  H01L29/66

Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.

公开(公告)号：US20160240357A1

公开(公告)日：2016-08-18

申请号：US14622397

申请日：2015-02-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Chien CHI ,  Hung-Wen SU ,  Pei-Hsuan LEE

IPC: H01J37/34 ,  C23C14/35 ,  C23C14/34

CPC classification number: H01J37/3447 ,  C23C14/046 ,  C23C14/35 ,  H01J37/3402

Abstract: A physical vapor deposition system includes a chamber, a cover plate, a pedestal, and a collimator. The cover plate is disposed on the chamber for holding a target. The pedestal is disposed in the chamber for supporting a wafer. The collimator is mounted between the cover plate and the pedestal. The collimator includes a plurality of sidewall sheets together forming a plurality of passages. At least one of the passages has an entrance and an exit opposite to the entrance. The entrance faces the cover plate, and the exit faces the pedestal. A thickness of one of the sidewall sheets at the entrance is thinner than a thickness of the sidewall sheet at the exit.

Abstract translation: 物理气相沉积系统包括腔室，盖板，基座和准直器。 盖板设置在用于保持目标的室上。 基座设置在用于支撑晶片的腔室中。 准直器安装在盖板和基座之间。 准直器包括一起形成多个通道的多个侧壁片。 至少一个通道具有入口对面的入口和出口。 入口面向盖板，出口面向基座。 入口处的侧壁片之一的厚度比出口处侧壁片的厚度薄。

公开(公告)号：US20190198403A1

公开(公告)日：2019-06-27

申请号：US15855080

申请日：2017-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Wei FANG ,  Jing-Sen WANG ,  Yuan-Yao CHANG ,  Wei-Ray LIN ,  Ting-Hua HSIEH ,  Pei-Hsuan LEE ,  Yu-Hsuan HUANG

IPC: H01L21/66 ,  G01N21/95 ,  G01N21/88 ,  G01N21/93 ,  G06T7/00

Abstract: A method for inline inspection during semiconductor wafer fabrication is provided. The method includes forming a plurality of test structures on a semiconductor wafer along two opposite directions. An offset distance between a sample feature and a target feature of each of the test structures increases gradually along the two opposite directions. The method further includes producing an image of the test structures. The method also includes performing image analysis of the image to recognize a position with an extreme of a gray level. In addition, the method includes calculating an overlay error according to the recognized position.

公开(公告)号：US20190164826A1

公开(公告)日：2019-05-30

申请号：US15964430

申请日：2018-04-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Tang WU ,  Pao-Sheng CHEN ,  Pei-Hsuan LEE ,  Szu-Hua WU ,  Chih-Chien CHI

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/67

Abstract: In a method for manufacturing a semiconductor device, a substrate is provided. Various first metal layers are formed on the substrate. A dielectric structure with through holes is formed over the first metal layers. The through holes expose the first metal layers. A pre-clean operation is performed on the dielectric structure and the first metal layers by using an alcohol base vapor and/or an aldehyde base vapor as a reduction agent. Conductors are formed on the first metal layers. In forming the conductors, the through holes are filled with the conductors.