公开(公告)号：US20250140667A1

公开(公告)日：2025-05-01

申请号：US18590271

申请日：2024-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chiang Chang ,  Hua-Wei Tseng ,  Ta-Hsuan Lin ,  Wei-Cheng Wu ,  Der-Chyang Yeh

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/522 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: In a semiconductor package having a redistribution structure, two or more semiconductor dies are connected to a first side of the redistribution structure and an encapsulant surrounds the two or more semiconductor dies. An integrated passive device (IPD) is connected on a second side of the redistribution structure. The second side is opposite to the first side and the IPD is electrically coupled to the redistribution structure. An interconnect device is connected on the second side of the redistribution structure and is electrically coupled to the redistribution structure. Two or more external connections are on the second side of the redistribution structure and are electrically coupled to the redistribution structure.

公开(公告)号：US20250125223A1

公开(公告)日：2025-04-17

申请号：US18415426

申请日：2024-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yu Lee ,  Ta-Hsuan Lin ,  Hua-Wei Tseng ,  Wei-Cheng Wu

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

Abstract: A method includes forming a metal pad, depositing a passivation layer on the metal pad, and planarizing the passivation layer, so that the passivation layer includes a planar top surface. The method further includes etching the passivation layer to form an opening in the passivation layer, wherein the metal pad is exposed to the opening, and forming a conductive via including a lower portion in the opening, and an upper portion higher than the passivation layer. A polymer layer is then dispensed to cover the conductive via.

公开(公告)号：US11682654B2

公开(公告)日：2023-06-20

申请号：US16718073

申请日：2019-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Der-Chyang Yeh ,  Li-Hsien Huang ,  Ta-Hsuan Lin ,  Ming-Shih Yeh

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3114 ,  H01L23/49822 ,  H01L23/49827

Abstract: A semiconductor structure includes a semiconductor structure includes a semiconductor die, an insulating encapsulation, a passivation layer and conductive elements. The semiconductor die includes a sensor device and a semiconductor substrate with a first region and a second region adjacent to the first region, and the sensor device is embedded in the semiconductor substrate within the first region. The insulating encapsulation laterally encapsulates the semiconductor die and covers a sidewall of the semiconductor die. The passivation layer is located on the semiconductor die, wherein a recess penetrates through the passivation layer over the first region and is overlapped with the sensor device. The conductive elements are located on the passivation layer over the second region and are electrically connected to the semiconductor die, wherein the passivation layer is between the insulating encapsulation and the conductive elements.

公开(公告)号：US20210183813A1

公开(公告)日：2021-06-17

申请号：US16718073

申请日：2019-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Der-Chyang Yeh ,  Li-Hsien Huang ,  Ta-Hsuan Lin ,  Ming-Shih Yeh

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor structure includes a semiconductor structure includes a semiconductor die, an insulating encapsulation, a passivation layer and conductive elements. The semiconductor die includes a sensor device and a semiconductor substrate with a first region and a second region adjacent to the first region, and the sensor device is embedded in the semiconductor substrate within the first region. The insulating encapsulation laterally encapsulates the semiconductor die and covers a sidewall of the semiconductor die. The passivation layer is located on the semiconductor die, wherein a recess penetrates through the passivation layer over the first region and is overlapped with the sensor device. The conductive elements are located on the passivation layer over the second region and are electrically connected to the semiconductor die, wherein the passivation layer is between the insulating encapsulation and the conductive elements.