公开(公告)号：US20230369456A1

公开(公告)日：2023-11-16

申请号：US18181678

申请日：2023-03-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Zhi-Chang Lin ,  Jung-Hung Chang ,  Shih-Cheng Chen ,  Chih-Hao Wang ,  Chien Ning Yao ,  Tsung-Han Chuang ,  Kuo-Cheng Chiang

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/775 ,  H01L29/423 ,  H01L29/786 ,  H01L29/417 ,  H01L21/8234

CPC分类号： H01L29/6656 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/66439 ,  H01L29/41733 ,  H01L21/823431 ,  H01L21/823412 ,  H01L21/823418

摘要： A semiconductor device with back-side contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second S/D regions, a stack of nanostructured semiconductor layers disposed adjacent to the first S/D region, a gate structure surrounding each of the nanostructured semiconductor layers, a first pair of spacers disposed on opposite sidewalls of the first S/D region, a second pair of spacers disposed on opposite sidewalls of the second S/D region, a third pair of spacers disposed on opposite sidewalls of the gate structure, a first contact structure disposed on a first surface of the first S/D region, and a second contact structure disposed on a second surface of the first S/D region. The first and second surfaces are opposite to each other. The first pair of spacers are disposed on opposite sidewalls of the second contact structure.

公开(公告)号：US20230420520A1

公开(公告)日：2023-12-28

申请号：US18150524

申请日：2023-01-05

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tsung-Han Chuang ,  Zhi-Chang Lin ,  Shih-Cheng Chen ,  Jung-Hung Chang ,  Chien Ning Yao ,  Kai-Lin Chuang ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC分类号： H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L21/02 ,  H01L29/66

CPC分类号： H01L29/0847 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L21/02532 ,  H01L21/02639 ,  H01L29/775

摘要： In an embodiment, a device includes: first nanostructures; a first undoped semiconductor layer contacting a first dummy region of the first nanostructures; a first spacer on the first undoped semiconductor layer; a first source/drain region on the first spacer, the first source/drain region contacting a first channel region of the first nanostructures; and a first gate structure wrapped around the first channel region and the first dummy region of the first nanostructures.

公开(公告)号：US20230178600A1

公开(公告)日：2023-06-08

申请号：US17663463

申请日：2022-05-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tsung-Han Chuang ,  Zhi-Chang Lin ,  Shih-Cheng Chen ,  Jung-Hung Chang ,  Chien Ning Yao ,  Kai-Lin Chuang ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC分类号： H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234

CPC分类号： H01L29/0665 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

摘要： A method for forming a semiconductor device structure is provided. The semiconductor device structure includes a plurality of first nanostructures stacked over a substrate in a vertical direction. The semiconductor device structure includes a first bottom layer formed adjacent to the first nanostructures, and a first insulating layer formed over the first bottom layer. The semiconductor device structure includes a first source/drain (S/D) structure formed over the first insulating layer, and the first insulating layer is in direct contact with one of the first nanostructures.

公开(公告)号：US20240304687A1

公开(公告)日：2024-09-12

申请号：US18232986

申请日：2023-08-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chien Ning Yao ,  Chia-Hao Chang ,  Shih-Cheng Chen ,  Chih-Hao Wang ,  Chia-Cheng Tsai ,  Kuo-Cheng Chiang ,  Zhi-Chang Lin ,  Jung-Hung Chang ,  Tsung-Han Chuang

IPC分类号： H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC分类号： H01L29/41775 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/775

摘要： A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes forming a polysilicon structure on a substrate, depositing a first spacer layer on the polysilicon structure, depositing a second spacer layer on the first spacer layer, forming a S/D region on the substrate, removing the second spacer layer, depositing a third spacer layer on the first spacer layer and on the S/D region, depositing an ESL on the third spacer layer, depositing an ILD layer on the etch stop layer, and replacing the polysilicon structure with a gate structure surrounding the nanostructured layer.

公开(公告)号：US12051736B2

公开(公告)日：2024-07-30

申请号：US17463365

申请日：2021-08-31

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tsung-Han Chuang ,  Zhi-Chang Lin ,  Shih-Cheng Chen ,  Jung-Hung Chang ,  Chien Ning Yao ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC分类号： H01L29/66553 ,  H01L21/0259 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4983 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

摘要： A device includes a substrate, a first nanostructure channel above the substrate and a second nanostructure channel between the first nanostructure channel and the substrate. An inner spacer is between the first nanostructure channel and the second nanostructure channel. A gate structure abuts the first nanostructure channel, the second nanostructure channel and the inner spacer. A liner layer is between the inner spacer and the gate structure.