公开(公告)号：US20210042460A1

公开(公告)日：2021-02-11

申请号：US16734487

申请日：2020-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Shen LIN ,  Ming-Hsien LIN ,  Wan-Yu LO ,  Meng-Xiang LEE

IPC: G06F30/3308 ,  G06F30/392

Abstract: Methods for analyzing electromigration (EM) in an integrated circuit (IC) are provided. The layout of the IC is obtained. A metal segment is selected from the layout according to the current simulation result of the IC. It is determined whether to relax the EM rule on the metal segment according to the number of vias over the metal segment in the layout. The vias are in contact with the metal segment.

公开(公告)号：US20140264924A1

公开(公告)日：2014-09-18

申请号：US13859797

申请日：2013-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yeh YU ,  Yuan-Te HOU ,  Chung-Min FU ,  Wen-Hao CHEN ,  Wan-Yu LO

IPC: H01L23/528 ,  H01L21/768

CPC classification number: H01L23/5286 ,  H01L21/768 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11881 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit structure includes a plurality of power or ground rails for an integrated circuit, the plurality of power or ground rails vertically separated on a plane, a plurality of functional cells between the plurality of power rails or between the plurality of ground rails or both, and a jumper connection between the vertically separated power rails or ground rails, the jumper connection within a vertically aligned gap among the plurality of functional cells. A method of mitigating IR drop and electromigration affects in an integrated circuit includes forming a plurality of power rails or ground rails, each of the power rails or ground rails on separate vertical levels of a plane of an integrated circuit layout and connecting with a jumper connection at least two power rails or two ground rails, the jumper connection within a vertically aligned gap among cells of the integrated circuit.

Abstract translation: 集成电路结构包括用于集成电路的多个电源或接地导轨，在平面上垂直分离的多个电源或接地导轨，多个电源轨之间或多个接地导轨之间或多个接地导轨之间的多个功能单元，或两者之间 以及在垂直分离的电源轨或接地轨之间的跨接连接，多个功能单元之间的垂直对齐的间隙内的跨接连接。 在集成电路中减轻IR滴落和电迁移影响的方法包括在集成电路布局的平面的不同的垂直级上形成多个电源轨或接地轨，每个电源轨或接地轨与跳线连接 至少两个电源轨或两个接地轨，所述跨接线连接在所述集成电路的单元之间的垂直对齐的间隙内。

公开(公告)号：US20170133321A9

公开(公告)日：2017-05-11

申请号：US13859797

申请日：2013-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yeh YU ,  Yuan-Te HOU ,  Chung-Min FU ,  Wen-Hao CHEN ,  Wan-Yu LO

IPC: H01L23/528 ,  H01L21/768

CPC classification number: H01L23/5286 ,  H01L21/768 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11881 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit structure includes a plurality of power or ground rails for an integrated circuit, the plurality of power or ground rails vertically separated on a plane, a plurality of functional cells between the plurality of power rails or between the plurality of ground rails or both, and a jumper connection between the vertically separated power rails or ground rails, the jumper connection within a vertically aligned gap among the plurality of functional cells. A method of mitigating IR drop and electromigration affects in an integrated circuit includes forming a plurality of power rails or ground rails, each of the power rails or ground rails on separate vertical levels of a plane of an integrated circuit layout and connecting with a jumper connection at least two power rails or two ground rails, the jumper connection within a vertically aligned gap among cells of the integrated circuit.