公开(公告)号：US20220384650A1

公开(公告)日：2022-12-01

申请号：US17876330

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Jen LAI ,  Yen-Ming CHEN ,  Tsung-Lin LEE

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/10 ,  H01L29/49 ,  H01L29/06 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/762

Abstract: The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.

公开(公告)号：US20240097033A1

公开(公告)日：2024-03-21

申请号：US18521584

申请日：2023-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Jen LAI ,  Yen-Ming CHEN ,  Tsung-Lin LEE

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/49

CPC classification number: H01L29/7843 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/28088 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/4966

Abstract: The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.