公开(公告)号：US20220384650A1

公开(公告)日：2022-12-01

申请号：US17876330

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Jen LAI ,  Yen-Ming CHEN ,  Tsung-Lin LEE

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/10 ,  H01L29/49 ,  H01L29/06 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/762

Abstract: The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.

公开(公告)号：US20180350971A1

公开(公告)日：2018-12-06

申请号：US16049273

申请日：2018-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Ching CHENG ,  Chih Chieh YEH ,  Cheng-Hsien WU ,  Hung-Li CHIANG ,  Jung-Piao CHIU ,  Tzu-Chiang CHEN ,  Tsung-Lin LEE ,  Yu-Lin YANG ,  I-Sheng CHEN

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66

Abstract: A semiconductor device includes a fin field effect transistor (FinFET). The FinFET includes a channel disposed on a fin, a gate disposed over the channel and a source and drain. The channel includes at least two pairs of a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. The first semiconductor layer has a different lattice constant than the second semiconductor layer. A thickness of the first semiconductor layer is three to ten times a thickness of the second semiconductor layer at least in one pair.

公开(公告)号：US20220367276A1

公开(公告)日：2022-11-17

申请号：US17876442

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hung WANG ,  Tsung-Lin LEE ,  Wen-Chih CHIANG ,  Kuan-Jung CHEN

IPC: H01L21/8249 ,  H01L27/06 ,  H01L21/02 ,  H01L21/3065

Abstract: Disclosed is a method for forming a crystalline protective polysilicon layer which does not create defective voids during subsequent processes so as to provide effective protection to devices underneath. In one embodiment, a method for forming a semiconductor device, includes: depositing a protective coating on a first polysilicon layer; forming an epitaxial layer on the protective coating; and depositing a second polysilicon layer over the epitaxial layer, wherein the protective coating comprises a third polysilicon layer, wherein the third polysilicon layer is deposited at a first temperature in a range of 600-700 degree Celsius, and wherein the third polysilicon layer in the protect coating is configured to protect the first polysilicon layer when the second polysilicon layer is etched.

公开(公告)号：US20180145076A1

公开(公告)日：2018-05-24

申请号：US15356004

申请日：2016-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh WANG ,  Zheng-Yang PAN ,  Shih-Chieh CHANG ,  Yi-Min HUANG ,  Shahaji B. MORE ,  Tsung-Lin LEE

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/78 ,  H01L21/762 ,  H01L29/66

Abstract: A fin field effect transistor (FinFET) device structure and method for forming the same are provided. The FinFET device structure includes a fin structure extending above a substrate. The fin structure includes a channel region, a portion of the channel region is made of silicon germanium (SiGe), and the silicon germanium (SiGe) has a gradient germanium (Ge) concentration. The FinFET device structure includes a gate structure formed on the channel region of the fin structure.

公开(公告)号：US20240222197A1

公开(公告)日：2024-07-04

申请号：US18609875

申请日：2024-03-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hung WANG ,  Tsung-Lin LEE ,  Wen-Chih CHIANG ,  Kuan-Jung CHEN

IPC: H01L21/8249 ,  H01L21/02 ,  H01L21/3065 ,  H01L27/06

CPC classification number: H01L21/8249 ,  H01L21/02164 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/3065 ,  H01L27/0623

Abstract: Disclosed is a method for forming a crystalline protective polysilicon layer which does not create defective voids during subsequent processes so as to provide effective protection to devices underneath. In one embodiment, a method for forming a semiconductor device, includes: depositing a protective coating on a first polysilicon layer; forming an epitaxial layer on the protective coating; and depositing a second polysilicon layer over the epitaxial layer, wherein the protective coating comprises a third polysilicon layer, wherein the third polysilicon layer is deposited at a first temperature in a range of 600-700 degree Celsius, and wherein the third polysilicon layer in the protect coating is configured to protect the first polysilicon layer when the second polysilicon layer is etched.

公开(公告)号：US20220238678A1

公开(公告)日：2022-07-28

申请号：US17465300

申请日：2021-09-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Lin LEE ,  Choh Fei YEAP ,  Da-Wen LIN ,  Chih Yeh

IPC: H01L29/423 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/786 ,  H01L29/66

Abstract: Methods include providing a first fin structure and a second fin structure each extending from a substrate. A first gate-all-around (GAA) transistor is formed on the first fin structure; the first GAA transistor has a channel region within a first plurality of nanostructures. A second GAA transistor is formed on the second fin structure; the second GAA transistor has a second channel region configuration. The second GAA transistor has a channel region within a second plurality of nanostructures. The second plurality of nanostructures is less than the first plurality of nanostructures.

公开(公告)号：US20180151717A1

公开(公告)日：2018-05-31

申请号：US15429861

申请日：2017-02-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Ching CHENG ,  Chih Chieh YEH ,  Cheng-Hsien WU ,  Hung-Li CHIANG ,  Jung-Piao CHIU ,  Tzu-Chiang CHEN ,  Tsung-Lin LEE ,  Yu-Lin YANG ,  I-Sheng CHEN

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7845

Abstract: A semiconductor device includes a fin field effect transistor (FinFET). The FinFET includes a channel disposed on a fin, a gate disposed over the channel and a source and drain. The channel includes at least two pairs of a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. The first semiconductor layer has a different lattice constant than the second semiconductor layer. A thickness of the first semiconductor layer is three to ten times a thickness of the second semiconductor layer at least in one pair.

公开(公告)号：US20180151564A1

公开(公告)日：2018-05-31

申请号：US15429844

申请日：2017-02-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tung Ying LEE ,  Chih Chieh YEH ,  Tsung-Lin LEE ,  Yee-Chia YEO ,  Meng-Hsuan HSIAO

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. A mask pattern is formed over the sacrificial layer. The sacrificial layer and the source/drain structure are patterned by using the mask pattern as an etching mask, thereby forming openings adjacent to the patterned sacrificial layer and source/drain structure. A dielectric layer is formed in the openings. After the dielectric layer is formed, the patterned sacrificial layer is removed to form a contact opening over the patterned source/drain structure. A conductive layer is formed in the contact opening.

公开(公告)号：US20180130802A1

公开(公告)日：2018-05-10

申请号：US15348652

申请日：2016-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh WANG ,  Zheng-Yang PAN ,  Yi-Min HUANG ,  Shih-Chieh CHANG ,  Tsung-Lin LEE

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/165 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L27/0928 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/42364 ,  H01L29/7851

Abstract: A fin field effect transistor (FinFET) device structure and method for forming the same are provided. The FinFET device structure includes a fin structure extending above a substrate, and the fin structure has a first portion and a second portion below the first portion, and the first portion and the second portion are made of different materials. The FinFET device structure includes an isolation structure formed on the substrate, and an interface between the first portion and the second portion of the fin structure is above a top surface of the isolation structure. The FinFET device structure includes a liner layer formed on sidewalls of the second portion of the fin structure.

公开(公告)号：US20160336319A1

公开(公告)日：2016-11-17

申请号：US14714229

申请日：2015-05-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Lin YANG ,  Chia-Cheng HO ,  Chih Chieh YEH ,  Cheng-Yi PENG ,  Tsung-Lin LEE

IPC: H01L27/092 ,  H01L29/267 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device includes forming a fin structure over a substrate and forming a first gate structure over a first portion of the fin structure. A first nitride layer is formed over a second portion of the fin structure. The first nitride layer is exposed to ultraviolet radiation. Source/drain regions are formed at the second portion of the fin structure.

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成翅片结构，并在翅片结构的第一部分上形成第一栅极结构。 在翅片结构的第二部分上形成第一氮化物层。 第一氮化物层暴露于紫外线辐射。 源极/漏极区域形成在鳍状结构的第二部分处。