公开(公告)号：US12234145B2

公开(公告)日：2025-02-25

申请号：US18513545

申请日：2023-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Wei Chang ,  Ya-Jen Sheuh ,  Ren-Dou Lee ,  Yi-Chih Chang ,  Yi-Hsun Chiu ,  Yuan-Hsin Chi

IPC: B81C1/00 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/66

Abstract: Methods for improving wafer bonding performance are disclosed herein. In some embodiments, a method for bonding a pair of semiconductor substrates is disclosed. The method includes: processing at least one of the pair of semiconductor substrates, and bonding the pair of semiconductor substrates together. Each of the pair of semiconductor substrates is processed by: performing at least one chemical vapor deposition (CVD), and performing at least one chemical mechanical polishing (CMP). One of the at least one CVD is performed after all CMP performed before bonding.

公开(公告)号：US11851325B2

公开(公告)日：2023-12-26

申请号：US16695673

申请日：2019-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Wei Chang ,  Ya-Jen Sheuh ,  Ren-Dou Lee ,  Yi-Chih Chang ,  Yi-Hsun Chiu ,  Yuan-Hsin Chi

IPC: B81C1/00 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/66

CPC classification number: B81C1/00238 ,  H01L21/02274 ,  H01L21/31053 ,  H01L22/12

Abstract: Methods for improving wafer bonding performance are disclosed herein. In some embodiments, a method for bonding a pair of semiconductor substrates is disclosed. The method includes: processing at least one of the pair of semiconductor substrates, and bonding the pair of semiconductor substrates together. Each of the pair of semiconductor substrates is processed by: performing at least one chemical vapor deposition (CVD), and performing at least one chemical mechanical polishing (CMP). One of the at least one CVD is performed after all CMP performed before bonding.

公开(公告)号：US12138735B2

公开(公告)日：2024-11-12

申请号：US16559472

申请日：2019-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chung Chen ,  Yi-Shao Lin ,  Sheng-Tai Peng ,  Ya-Jen Sheuh ,  Hung-Lin Chen ,  Ren-Dou Lee

IPC: B24B37/20 ,  B24B37/013 ,  B24B37/04 ,  C09G1/02

Abstract: Described herein are multi-layered windows for use in chemical-mechanical planarization (CMP) systems and CMP processes. The multi-layered windows of the present disclosure include a transparent structural layer and a hydrophilic surfactant applied to at least a portion of at least one surface of the transparent structural layer. Such multi-layered windows may be in the polishing pad, the platen, or both.

公开(公告)号：US20200164482A1

公开(公告)日：2020-05-28

申请号：US16559472

申请日：2019-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chung Chen ,  Yi-Shao Lin ,  Sheng-Tai Peng ,  Ya-Jen Sheuh ,  Hung-Lin Chen ,  Ren-Dou Lee

IPC: B24B37/20 ,  B24B37/013 ,  C09G1/02 ,  B24B37/04

Abstract: Described herein are multi-layered windows for use in chemical-mechanical planarization (CMP) systems and CMP processes. The multi-layered windows of the present disclosure include a transparent structural layer and a hydrophilic surfactant applied to at least a portion of at least one surface of the transparent structural layer. Such multi-layered windows may be in the polishing pad, the platen, or both.