公开(公告)号：US09865609B2

公开(公告)日：2018-01-09

申请号：US15008748

申请日：2016-01-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Lin Chen ,  Shyh-Wei Cheng ,  Che-Jung Chu

IPC: H01L27/115 ,  H01L21/28 ,  H01L27/11521 ,  G11C16/04

CPC classification number: H01L27/11521 ,  G11C16/0433 ,  G11C17/08 ,  H01L21/28273 ,  H01L27/11524

Abstract: A one-time programmable (OTP) memory cell with floating gate shielding is provided. A pair of transistors is arranged on a semiconductor substrate and electrically coupled in series, where the transistors comprise a floating gate. An interconnect structure overlies the pair of transistors. A shield is arranged in the interconnect structure, directly over the floating gate. The shield is configured to block ions in the interconnect structure from moving to the floating gate. A method for manufacturing an OTP memory cell with floating gate shielding is also provided.

公开(公告)号：US20170221910A1

公开(公告)日：2017-08-03

申请号：US15008748

申请日：2016-01-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Lin Chen ,  Shyh-Wei Cheng ,  Che-Jung Chu

IPC: H01L27/115 ,  G11C16/04 ,  H01L21/28

CPC classification number: H01L27/11521 ,  G11C16/0433 ,  G11C17/08 ,  H01L21/28273 ,  H01L27/11524

Abstract: A one-time programmable (OTP) memory cell with floating gate shielding is provided. A pair of transistors is arranged on a semiconductor substrate and electrically coupled in series, where the transistors comprise a floating gate. An interconnect structure overlies the pair of transistors. A shield is arranged in the interconnect structure, directly over the floating gate. The shield is configured to block ions in the interconnect structure from moving to the floating gate. A method for manufacturing an OTP memory cell with floating gate shielding is also provided

公开(公告)号：US10586705B2

公开(公告)日：2020-03-10

申请号：US15904041

申请日：2018-02-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Lin Chen ,  Shiuan-Jeng Lin ,  Wen-Chih Chiang ,  Po-Ming Chen ,  Tza-Hao Wang

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/51 ,  H01L21/3115 ,  H01L29/788 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/266

Abstract: A non-volatile memory cell is disclosed. In one example, the non-volatile memory cell includes: a substrate; a first oxide layer over the substrate; a floating gate over the first oxide layer; a second oxide layer over the floating gate; and a control gate at least partially over the second oxide layer. At least one of the first oxide layer and the second oxide layer comprises fluorine.

公开(公告)号：US09966427B2

公开(公告)日：2018-05-08

申请号：US15154027

申请日：2016-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shyh-Wei Cheng ,  Hung-Lin Chen ,  Jui-Chun Weng ,  Shiuan-Jeng Lin ,  Tian Sheng Lin ,  Yu-Jui Wu ,  Albion Pan ,  Bob Sun

IPC: H01L49/02 ,  H01L23/522 ,  H01L21/3213 ,  H01L21/311

CPC classification number: H01L28/75 ,  H01L21/31111 ,  H01L21/32139 ,  H01L23/5223

Abstract: A method for manufacturing a metal-insulator-metal (MIM) capacitor with a top electrode that is free of sidewall damage is provided. A bottom electrode layer is formed with a first material. An inter-electrode dielectric layer is formed over the bottom electrode layer. A top electrode layer is formed over the inter-electrode dielectric layer and without the first material. A first etch is performed into the top electrode layer and the inter-electrode dielectric layer to form a top electrode. A second etch into the bottom electrode layer to form a bottom electrode. The present application is also directed towards a MIM capacitor resulting from performing the method.

公开(公告)号：US20170330931A1

公开(公告)日：2017-11-16

申请号：US15154027

申请日：2016-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shyh-Wei Cheng ,  Hung-Lin Chen ,  Jui-Chun Weng ,  Shiuan-Jeng Lin ,  Tian Sheng Lin ,  Yu-Jui Wu ,  Albion Pan ,  Bob Sun

IPC: H01L49/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/522

CPC classification number: H01L28/75 ,  H01L21/31111 ,  H01L21/32139 ,  H01L23/5223

Abstract: A method for manufacturing a metal-insulator-metal (MIM) capacitor with a top electrode that is free of sidewall damage is provided. A bottom electrode layer is formed with a first material. An inter-electrode dielectric layer is formed over the bottom electrode layer. A top electrode layer is formed over the inter-electrode dielectric layer and without the first material. A first etch is performed into the top electrode layer and the inter-electrode dielectric layer to form a top electrode. A second etch into the bottom electrode layer to form a bottom electrode. The present application is also directed towards a MIM capacitor resulting from performing the method.

公开(公告)号：US12138735B2

公开(公告)日：2024-11-12

申请号：US16559472

申请日：2019-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chung Chen ,  Yi-Shao Lin ,  Sheng-Tai Peng ,  Ya-Jen Sheuh ,  Hung-Lin Chen ,  Ren-Dou Lee

IPC: B24B37/20 ,  B24B37/013 ,  B24B37/04 ,  C09G1/02

Abstract: Described herein are multi-layered windows for use in chemical-mechanical planarization (CMP) systems and CMP processes. The multi-layered windows of the present disclosure include a transparent structural layer and a hydrophilic surfactant applied to at least a portion of at least one surface of the transparent structural layer. Such multi-layered windows may be in the polishing pad, the platen, or both.

公开(公告)号：US20200164482A1

公开(公告)日：2020-05-28

申请号：US16559472

申请日：2019-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chung Chen ,  Yi-Shao Lin ,  Sheng-Tai Peng ,  Ya-Jen Sheuh ,  Hung-Lin Chen ,  Ren-Dou Lee

IPC: B24B37/20 ,  B24B37/013 ,  C09G1/02 ,  B24B37/04

Abstract: Described herein are multi-layered windows for use in chemical-mechanical planarization (CMP) systems and CMP processes. The multi-layered windows of the present disclosure include a transparent structural layer and a hydrophilic surfactant applied to at least a portion of at least one surface of the transparent structural layer. Such multi-layered windows may be in the polishing pad, the platen, or both.