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公开(公告)号：US10049851B2
公开(公告)日：2018-08-14
申请号：US15143246
申请日：2016-04-29
发明人： Jensen Yang , Shy-Jay Lin , Yen-Hao Huang
IPC分类号： H01J37/317 , H01J37/00
摘要： A system includes a digital pattern generator (DPG) having a plurality of pixels that are dynamically and individually controllable; a switching device that is coupled to the DPG, the switching device configured to route a packet to the DPG so as to control at least one of the pixels, the switching device further comprising: a plurality of input buffers configured to receive and store the packet through a transmission line; a plurality of output buffers; a plurality of memory devices, wherein each of the plurality of memory devices is associated with one of the plurality of output buffers; and a scheduling engine that is coupled to the plurality of input buffers, the plurality of output buffers, and the plurality of memory devices and is configured to determine a routing path for the packet stored in one of the input buffers based on an availability of the output buffers and a vacancy level the memory devices.
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公开(公告)号：US10804066B2
公开(公告)日：2020-10-13
申请号：US16601417
申请日：2019-10-14
发明人： Jensen Yang , Shy-Jay Lin , Yen-Hao Huang
IPC分类号： H01J37/00 , H01J37/31 , H01J37/317
摘要： A method for routing data for an e-beam writer includes, with a switching device of the e-beam writer, receiving a packet. The method further includes, with a scheduling engine of the switching device, routing the packet to one of a plurality of output buffers, wherein the routing is based on availabilities of the plurality of output buffers and vacancy levels of memory devices associated with the plurality of output buffers. The method further includes, with the switching device, outputting the packet from an output port associated with a memory device to which the packet is routed.
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公开(公告)号：US20190139733A1
公开(公告)日：2019-05-09
申请号：US16103616
申请日：2018-08-14
发明人： Jensen Yang , Shy-Jay Lin , Yen-Hao Huang
IPC分类号： H01J37/00 , H01J37/317
CPC分类号： H01J37/00 , H01J37/3174 , H01J2237/31762
摘要： A method includes receiving, by an input buffer of a switching device, a packet, determining, by a scheduling engine of the switching device, a destination output buffer for the packet, receiving, by the scheduling engine of the switching device, an availability of the destination output buffer and a vacancy level of a memory device that is associated with the destination output buffer, and based on the availability of the destination output buffer and the vacancy level of the memory device, determining, by the scheduling engine of the switching device, a routing destination of the packet. The routing destination includes the input buffer, the destination output buffer, and the memory device.
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公开(公告)号：US11411571B2
公开(公告)日：2022-08-09
申请号：US17330818
申请日：2021-05-26
发明人： Sandeep Kumar Goel , Ji-Jan Chen , Stanley John , Yun-Han Lee , Yen-Hao Huang
摘要： A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.
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公开(公告)号：US10256828B2
公开(公告)日：2019-04-09
申请号：US15711201
申请日：2017-09-21
发明人： Sandeep Kumar Goel , Ji-Jan Chen , Stanley John , Yun-Han Lee , Yen-Hao Huang
摘要： A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.
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公开(公告)号：US10680627B2
公开(公告)日：2020-06-09
申请号：US16372706
申请日：2019-04-02
发明人： Sandeep Kumar Goel , Ji-Jan Chen , Stanley John , Yun-Han Lee , Yen-Hao Huang
摘要： A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.
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公开(公告)号：US20200043692A1
公开(公告)日：2020-02-06
申请号：US16601417
申请日：2019-10-14
发明人： Jensen Yang , Shy-Jay Lin , Yen-Hao Huang
IPC分类号： H01J37/00 , H01J37/317
摘要： A method for routing data for an e-beam writer includes, with a switching device of the e-beam writer, receiving a packet. The method further includes, with a scheduling engine of the switching device, routing the packet to one of a plurality of output buffers, wherein the routing is based on availabilities of the plurality of output buffers and vacancy levels of memory devices associated with the plurality of output buffers. The method further includes, with the switching device, outputting the packet from an output port associated with a memory device to which the packet is routed.
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公开(公告)号：US11025261B2
公开(公告)日：2021-06-01
申请号：US16894607
申请日：2020-06-05
发明人： Sandeep Kumar Goel , Ji-Jan Chen , Stanley John , Yun-Han Lee , Yen-Hao Huang
摘要： A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.
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公开(公告)号：US10446358B2
公开(公告)日：2019-10-15
申请号：US16103616
申请日：2018-08-14
发明人： Jensen Yang , Shy-Jay Lin , Yen-Hao Huang
IPC分类号： H01J37/00 , H01J37/317
摘要： A method includes receiving, by an input buffer of a switching device, a packet, determining, by a scheduling engine of the switching device, a destination output buffer for the packet, receiving, by the scheduling engine of the switching device, an availability of the destination output buffer and a vacancy level of a memory device that is associated with the destination output buffer, and based on the availability of the destination output buffer and the vacancy level of the memory device, determining, by the scheduling engine of the switching device, a routing destination of the packet. The routing destination includes the input buffer, the destination output buffer, and the memory device.
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公开(公告)号：US20190229737A1
公开(公告)日：2019-07-25
申请号：US16372706
申请日：2019-04-02
发明人： Sandeep Kumar GOEL , Ji-Jan Chen , Stanley John , Yun-Han Lee , Yen-Hao Huang
摘要： A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.
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