公开(公告)号：US10170414B2

公开(公告)日：2019-01-01

申请号：US15693083

申请日：2017-08-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Hsin Hu ,  Yu-Chiun Lin ,  Yi-Hsuan Chung ,  Chung-Peng Hsieh ,  Chung-Chieh Yang ,  Po-Nien Chen

IPC: H01L23/522 ,  H01L49/02 ,  H01L27/11582

Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.

公开(公告)号：US12033937B2

公开(公告)日：2024-07-09

申请号：US17099002

申请日：2020-11-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Hsin Hu ,  Yu-Chiun Lin ,  Yi-Hsuan Chung ,  Chung-Peng Hsieh ,  Chung-Chieh Yang ,  Po-Nien Chen

IPC: H01L23/522 ,  H01L49/02 ,  H10B43/27

CPC classification number: H01L23/5228 ,  H01L28/00 ,  H01L28/24 ,  H10B43/27

Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.

公开(公告)号：US09773731B2

公开(公告)日：2017-09-26

申请号：US15009500

申请日：2016-01-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Hsin Hu ,  Yu-Chiun Lin ,  Yi-Hsuan Chung ,  Chung-Peng Hsieh ,  Chung-Chieh Yang ,  Po-Nien Chen

IPC: H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5228 ,  H01L27/11582 ,  H01L28/00 ,  H01L28/24

Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.

公开(公告)号：US11942375B2

公开(公告)日：2024-03-26

申请号：US17404443

申请日：2021-08-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsing-Hui Hsu ,  Po-Nien Chen ,  Yi-Hsuan Chung ,  Bo-Shiuan Shie ,  Chih-Yung Lin

IPC: H01L21/8238 ,  H01L21/02 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/02532 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823871 ,  H01L27/0924 ,  H01L27/0928 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/823892 ,  H01L29/7848

Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a first semiconductor fin and a second semiconductor fin over a semiconductor substrate. The second semiconductor fin is wider than the first semiconductor fin. The method also includes forming a gate stack over the semiconductor substrate, and the gate stack extends across the first semiconductor fin and the second semiconductor fin. The method further includes forming a first source/drain structure on the first semiconductor fin, and the first source/drain structure is p-type doped. In addition, the method includes forming a second source/drain structure on the second semiconductor fin, and the second source/drain structure is n-type doped.

公开(公告)号：US11094597B2

公开(公告)日：2021-08-17

申请号：US16526692

申请日：2019-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsing-Hui Hsu ,  Po-Nien Chen ,  Yi-Hsuan Chung ,  Bo-Shiuan Shie ,  Chih-Yung Lin

IPC: H01L29/49 ,  H01L21/84 ,  H01L21/324 ,  H01L29/78 ,  H01L29/51 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/02 ,  H01L27/092

Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a first semiconductor fin and a second semiconductor fin over a semiconductor substrate. The second semiconductor fin is wider than the first semiconductor fin. The method also includes forming a gate stack over the semiconductor substrate, and the gate stack extends across the first semiconductor fin and the second semiconductor fin. The method further includes forming a first source/drain structure on the first semiconductor fin, and the first source/drain structure is p-type doped. In addition, the method includes forming a second source/drain structure on the second semiconductor fin, and the second source/drain structure is n-type doped.

公开(公告)号：US20210375697A1

公开(公告)日：2021-12-02

申请号：US17404443

申请日：2021-08-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsing-Hui Hsu ,  Po-Nien Chen ,  Yi-Hsuan Chung ,  Bo-Shiuan Shie ,  Chih-Yung Lin

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L27/092

Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a first semiconductor fin and a second semiconductor fin over a semiconductor substrate. The second semiconductor fin is wider than the first semiconductor fin. The method also includes forming a gate stack over the semiconductor substrate, and the gate stack extends across the first semiconductor fin and the second semiconductor fin. The method further includes forming a first source/drain structure on the first semiconductor fin, and the first source/drain structure is p-type doped. In addition, the method includes forming a second source/drain structure on the second semiconductor fin, and the second source/drain structure is n-type doped.