公开(公告)号：US12087761B2

公开(公告)日：2024-09-10

申请号：US18210472

申请日：2023-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Yeh ,  Wun-Jie Lin ,  Jam-Wem Lee

IPC: H01L27/02 ,  H01L23/522 ,  H01L23/535 ,  H02H9/04

CPC classification number: H01L27/0288 ,  H01L23/5223 ,  H01L23/5228 ,  H01L23/535 ,  H01L27/0285 ,  H01L27/0292 ,  H02H9/046

Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: a plurality of transistors patterned on a semiconductor substrate during a front-end-of-line (FEOL) process, metal interconnects formed on top of the plurality of transistors during a back-end-of-line (BEOL) process and configured to interconnect the plurality of transistors, and a plurality of passive components formed under the semiconductor substrate in a backside layer during a backside a back-end-of-line (B-BEOL) process, wherein the plurality of passive components are connected to the plurality of transistors through a plurality of vias.

公开(公告)号：US11862626B2

公开(公告)日：2024-01-02

申请号：US17191496

申请日：2021-03-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Yeh

IPC: H01L27/02 ,  H02H9/04

CPC classification number: H01L27/0266 ,  H01L27/0288 ,  H02H9/046

Abstract: An apparatus for providing electrostatic discharge (ESD) immunity and a method for fabricating the same are disclosed herein. The apparatus comprises a field effect transistor (FET) formed on a semiconductor substrate in a front-end-of-line (FEOL) layer during an FEOL process, a metal interconnect layer formed on top of the FEOL layer during a back-end-of-line (BEOL) process, wherein the metal interconnect layer comprises a plurality interconnects configured to interconnect the FET to a plurality of components formed on the semiconductor substrate, a power delivery network (PDN) formed under the semiconductor substrate in a backside layer during a backside back-end-of-line (B-BEOL) process, and a through substrate resistive component formed between the FEOL and B-BEOL layers, wherein a first contact of the through substrate resistive component is connected to a drain terminal of the FET and second contact is connected, through the PDN, to a power supply rail.

公开(公告)号：US11728330B2

公开(公告)日：2023-08-15

申请号：US17219495

申请日：2021-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Yeh ,  Wun-Jie Lin ,  Jam-Wem Lee

IPC: H01L27/02 ,  H01L23/522 ,  H01L23/535 ,  H02H9/04

CPC classification number: H01L27/0288 ,  H01L23/5223 ,  H01L23/5228 ,  H01L23/535 ,  H01L27/0285 ,  H01L27/0292 ,  H02H9/046

Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: a plurality of transistors patterned on a semiconductor substrate during a front-end-of-line (FEOL) process, metal interconnects formed on top of the plurality of transistors during a back-end-of-line (BEOL) process and configured to interconnect the plurality of transistors, and a plurality of passive components formed under the semiconductor substrate in a backside layer during a backside a back-end-of-line (B-BEOL) process, wherein the plurality of passive components are connected to the plurality of transistors through a plurality of vias.