公开(公告)号：US12087761B2

公开(公告)日：2024-09-10

申请号：US18210472

申请日：2023-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Yeh ,  Wun-Jie Lin ,  Jam-Wem Lee

IPC: H01L27/02 ,  H01L23/522 ,  H01L23/535 ,  H02H9/04

CPC classification number: H01L27/0288 ,  H01L23/5223 ,  H01L23/5228 ,  H01L23/535 ,  H01L27/0285 ,  H01L27/0292 ,  H02H9/046

Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: a plurality of transistors patterned on a semiconductor substrate during a front-end-of-line (FEOL) process, metal interconnects formed on top of the plurality of transistors during a back-end-of-line (BEOL) process and configured to interconnect the plurality of transistors, and a plurality of passive components formed under the semiconductor substrate in a backside layer during a backside a back-end-of-line (B-BEOL) process, wherein the plurality of passive components are connected to the plurality of transistors through a plurality of vias.

公开(公告)号：US12027525B2

公开(公告)日：2024-07-02

申请号：US16940930

申请日：2020-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien Yao Huang ,  Wun-Jie Lin ,  Kuo-Ji Chen

IPC: H01L27/11 ,  G06F30/392 ,  H01L21/265 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/118 ,  G06F117/02

CPC classification number: H01L27/11807 ,  G06F30/392 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823892 ,  H01L27/0207 ,  G06F2117/02 ,  H01L2027/1189

Abstract: An integrated circuit (IC) device includes a plurality of TAP cells arranged at intervals in a first direction and a second direction transverse to the first direction. The plurality of TAP cells includes at least one first TAP cell. The first TAP cell includes two first end areas and a first middle area arranged consecutively in the second direction. The first middle area includes a first dopant of a first type implanted in a first well region of the first type. The first end areas are arranged on opposite sides of the first middle area in the second direction. Each of the first end areas includes a second dopant of a second type implanted in the first well region, the second type different from the first type.

公开(公告)号：US20230395534A1

公开(公告)日：2023-12-07

申请号：US18232739

申请日：2023-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tao-Yi HUNG ,  Wun-Jie Lin ,  Jam-Wem Lee ,  Kuo-Ji Chen

IPC: H01L23/60 ,  H01L27/02 ,  H02H9/04

CPC classification number: H01L23/60 ,  H01L27/0266 ,  H01L27/0292 ,  H02H9/046

Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus comprises: an internal circuit formed in a first wafer; an array of electrostatic discharge (ESD) circuits formed in a second wafer, wherein the ESD circuits include a plurality of ESD protection devices each coupled to a corresponding switch and configured to protect the internal circuit from a transient ESD event; and a switch controller in the second wafer, wherein the switch controller is configured to control, based on a control signal from the first wafer, each of the plurality of ESD protection devices to be activated or deactivated by the corresponding switch, and wherein the first wafer is bonded to the second wafer.

公开(公告)号：US11646317B2

公开(公告)日：2023-05-09

申请号：US17024351

申请日：2020-09-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien Yao Huang ,  Wun-Jie Lin ,  Kuo-Ji Chen

IPC: H01L27/118 ,  H01L27/02 ,  H01L27/092 ,  G06F30/392 ,  G06F119/06

CPC classification number: H01L27/11807 ,  G06F30/392 ,  H01L27/0207 ,  H01L27/0921 ,  G06F2119/06 ,  H01L27/0924 ,  H01L2027/1189 ,  H01L2027/11861

Abstract: An integrated circuit (IC) device includes a plurality of first TAP cells of a first semiconductor type, and a plurality of second TAP cells of a second semiconductor type different from the first semiconductor type. The plurality of first TAP cells is arranged in at least two columns, the at least two columns adjacent each other in a first direction and extending in a second direction transverse to the first direction. Each of the plurality of first TAP cells has a first length in the first direction. The plurality of second TAP cells includes at least one second TAP cell extending in the first direction between the at least two columns over a second length greater than the first length of each of the plurality of first TAP cells in the first direction.

公开(公告)号：US10971495B2

公开(公告)日：2021-04-06

申请号：US16591064

申请日：2019-10-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Yao Huang ,  Wun-Jie Lin ,  Chia-Wei Hsu ,  Yu-Ti Su

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/94 ,  H01L27/02 ,  H01L27/08 ,  H01L29/861

Abstract: A capacitor cell is provided. A first PMOS transistor is coupled between a power supply and a first node, and has a gate connected to a second node. A first NMOS transistor is coupled between a ground and the second node, and has a gate connected to the first node. A second PMOS transistor is coupled between the second node and the first node, and has a gate connected to the second node. A second NMOS transistor has a drain connected to the first node, a gate connected to the first node, and a source connected to the ground or the second node. The first and second PMOS transistors and the first and second NMOS transistors are arranged in the same row. The second PMOS transistor is disposed between the first PMOS transistor and the first and second NMOS transistors.

公开(公告)号：US12176341B2

公开(公告)日：2024-12-24

申请号：US18513544

申请日：2023-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tao-Yi Hung ,  Wun-Jie Lin ,  Jam-Wem Lee ,  Kuo-Ji Chen

IPC: H01L27/02 ,  H02H9/04

Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: an internal circuit patterned in a device wafer and electrically coupled between a first node and a second node, an array of electrostatic discharge (ESD) circuits patterned in a carrier wafer, where the ESD circuits are electrically coupled between a first node and a second node and configured to protect the internal circuit from transient ESD events, and where the device wafer is bonded to the carrier wafer.

公开(公告)号：US11569223B2

公开(公告)日：2023-01-31

申请号：US17086076

申请日：2020-10-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tao-Yi Hung ,  Wun-Jie Lin ,  Jam-Wem Lee ,  Kuo-Ji Chen ,  Chia-En Huang

IPC: H01L27/02 ,  H01L21/8238 ,  H01L27/092

Abstract: A method for fabricating an integrated circuit is provided. The method includes etching a first recess in a semiconductor structure; forming a first doped epitaxial feature in the first recess; and forming a second doped epitaxial feature over the first doped epitaxial feature, wherein the second doped epitaxial feature has a conductive type opposite to a conductive type of the first doped epitaxial feature.

公开(公告)号：US11380673B2

公开(公告)日：2022-07-05

申请号：US17107694

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wun-Jie Lin ,  Han-Jen Yang ,  Yu-Ti Su

IPC: H01L27/02 ,  H01L29/66 ,  H02H9/04 ,  H01L27/088 ,  H01L29/10 ,  H01L21/8234 ,  H01L23/60 ,  H01L21/28

Abstract: An Electro-Static Discharge (ESD) includes a first well having a first conductivity type on a substrate. The device further includes a second well within the first well. The second well has a second conductivity type. The device further includes a third well within the first well. The third well has the second conductivity type. The device further includes a first gate device disposed over the first well, a plurality of active regions between the first gate device and the dummy gate, and a dummy gate disposed within a space between the active regions. The dummy gate is positioned over a space between the second and third wells.

公开(公告)号：US10854595B2

公开(公告)日：2020-12-01

申请号：US16219747

申请日：2018-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wun-Jie Lin ,  Han-Jen Yang ,  Yu-Ti Su

IPC: H01L27/02 ,  H01L21/28 ,  H02H9/04 ,  H01L27/088 ,  H01L29/10 ,  H01L21/8234 ,  H01L29/66 ,  H01L23/60

Abstract: An Electro-Static Discharge (ESD) includes a first well having a first conductivity type on a substrate. The device further includes a second well within the first well. The second well has a second conductivity type. The device further includes a third well within the first well. The third well has the second conductivity type. The device further includes a first gate device disposed over the first well, a plurality of active regions between the first gate device and the dummy gate, and a dummy gate disposed within a space between the active regions. The dummy gate is positioned over a space between the second and third wells.

公开(公告)号：US11855076B2

公开(公告)日：2023-12-26

申请号：US17150782

申请日：2021-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tao-Yi Hung ,  Wun-Jie Lin ,  Jam-Wem Lee ,  Kuo-Ji Chen

IPC: H01L27/02 ,  H02H9/04

CPC classification number: H01L27/0288 ,  H01L27/0255 ,  H01L27/0266 ,  H02H9/046

Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: an internal circuit patterned in a device wafer and electrically coupled between a first node and a second node, an array of electrostatic discharge (ESD) circuits patterned in a carrier wafer, where the ESD circuits are electrically coupled between a first node and a second node and configured to protect the internal circuit from transient ESD events, and where the device wafer is bonded to the carrier wafer.