公开(公告)号：US20250167075A1

公开(公告)日：2025-05-22

申请号：US18512194

申请日：2023-11-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Jen Lien ,  Chen-Hua Yu ,  Cheng-Chieh Hsieh ,  Kuo-Chung Yee ,  Hung-Yi Kuo ,  Ke-Han Shen

IPC: H01L23/473 ,  H01L21/48 ,  H01L23/00 ,  H01L23/48

Abstract: Semiconductor devices and methods of manufacture are presented herein. In accordance with some embodiments, a device includes a first semiconductor device, the first semiconductor device including a first interconnect structure, an integrated cooling structure bonded to the first interconnect structure, wherein the integrated cooling structure is configured for a working fluid to enter and exit the integrated cooling structure, a second semiconductor device including a second interconnect structure, the second semiconductor device bonded to the integrated cooling structure opposite the first interconnect structure, and a plurality of through substrate vias extending through the integrated cooling structure, wherein the plurality of through substrate vias electrically couple the first semiconductor device to the second semiconductor device.

公开(公告)号：US20240162109A1

公开(公告)日：2024-05-16

申请号：US18152615

申请日：2023-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Yi Kuo ,  Chen-Hua Yu ,  Kuo-Chung Yee ,  Yu-Jen Lien ,  Ke-Han Shen ,  Wei-Kong Sheng ,  Chung-Shi Liu ,  Szu-Wei Lu ,  Tsung-Fu Tsai ,  Chung-Ju Lee ,  Chih-Ming Ke

IPC: H01L23/367 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H10B80/00

CPC classification number: H01L23/3677 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/3736 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H10B80/00 ,  H01L2224/16225 ,  H01L2224/29124 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/29172 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253

Abstract: In an embodiment, a package includes an integrated circuit device attached to a substrate; an encapsulant disposed over the substrate and laterally around the integrated circuit device, wherein a top surface of the encapsulant is coplanar with the top surface of the integrated circuit device; and a heat dissipation structure disposed over the integrated circuit device and the encapsulant, wherein the heat dissipation structure includes a spreading layer disposed over the encapsulant and the integrated circuit device, wherein the spreading layer includes a plurality of islands, wherein at least a portion of the islands are arranged as lines extending in a first direction in a plan view; a plurality of pillars disposed over the islands of the spreading layer; and nanostructures disposed over the pillars.