公开(公告)号：US11048161B2

公开(公告)日：2021-06-29

申请号：US16727994

申请日：2019-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chun Wang ,  Chi-Ping Liu ,  Feng-Ju Chang ,  Ching-Hsu Chang ,  Wen Hao Liu ,  Chia-Feng Yeh ,  Ming-Hui Chih ,  Cheng Kun Tsai ,  Wei-Chen Chien ,  Wen-Chun Huang ,  Yu-Po Tang

IPC: G03F1/36 ,  G06F30/398

Abstract: Optical proximity correction (OPC) based computational lithography techniques are disclosed herein for enhancing lithography printability. An exemplary mask optimization method includes receiving an integrated circuit (IC) design layout having an IC pattern; generating target points for a contour corresponding with the IC pattern based on a target placement model, wherein the target placement model is selected based on a classification of the IC pattern; and performing an OPC on the IC pattern using the target points, thereby generating a modified IC design layout. The method can further include fabricating a mask based on the modified IC design layout. The OPC can select an OPC model based on the classification of the IC pattern. The OPC model can weight the target placement model.

公开(公告)号：US10527928B2

公开(公告)日：2020-01-07

申请号：US15653784

申请日：2017-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chun Wang ,  Chi-Ping Liu ,  Feng-Ju Chang ,  Ching-Hsu Chang ,  Wen Hao Liu ,  Chia-Feng Yeh ,  Ming-Hui Chih ,  Cheng Kun Tsai ,  Wei-Chen Chien ,  Wen-Chun Huang ,  Yu-Po Tang

IPC: G06F17/50 ,  G03F1/36

Abstract: Optical proximity correction (OPC) based computational lithography techniques are disclosed herein for enhancing lithography printability. An exemplary mask optimization method includes receiving an integrated circuit (IC) design layout having an IC pattern; generating target points for a contour corresponding with the IC pattern based on a target placement model, wherein the target placement model is selected based on a classification of the IC pattern; and performing an OPC on the IC pattern using the target points, thereby generating a modified IC design layout. The method can further include fabricating a mask based on the modified IC design layout. The OPC can select an OPC model based on the classification of the IC pattern. The OPC model can weight the target placement model.

公开(公告)号：US20180173090A1

公开(公告)日：2018-06-21

申请号：US15653784

申请日：2017-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chun Wang ,  Chi-Ping Liu ,  Feng-Ju Chang ,  Ching-Hsu Chang ,  Wen Hao Liu ,  Chia-Feng Yeh ,  Ming-Hui Chih ,  Cheng Kun Tsai ,  Wei-Chen Chien ,  Wen-Chun Huang ,  Yu-Po Tang

IPC: G03F1/36 ,  G06F17/50

CPC classification number: G03F1/36 ,  G06F17/5081

Abstract: Optical proximity correction (OPC) based computational lithography techniques are disclosed herein for enhancing lithography printability. An exemplary mask optimization method includes receiving an integrated circuit (IC) design layout having an IC pattern; generating target points for a contour corresponding with the IC pattern based on a target placement model, wherein the target placement model is selected based on a classification of the IC pattern; and performing an OPC on the IC pattern using the target points, thereby generating a modified IC design layout. The method can further include fabricating a mask based on the modified IC design layout. The OPC can select an OPC model based on the classification of the IC pattern. The OPC model can weight the target placement model.