公开(公告)号：US20190094710A1

公开(公告)日：2019-03-28

申请号：US15715943

申请日：2017-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chun Wang ,  Chi-Ping Liu ,  Cheng Kun Tsai ,  Wei-Chen Chien ,  Wen-Chun Huang

IPC: G03F7/20 ,  G06F17/50

Abstract: Examples of optical proximity correction (OPC) based computational lithography techniques are disclosed herein. An exemplary method includes receiving an IC design layout that includes an IC feature, the IC feature specifying a mask feature for selectively exposing to radiation a portion of a photoresist disposed on a substrate; determining topographical information of an underlying layer disposed on the substrate between the photoresist and the substrate; performing an OPC process on the IC feature to generate a modified IC feature; and providing a modified IC design layout including the modified IC feature for fabricating a mask based on the modified IC design layout. The OPC process may use the topographical information of the underlying layer to compensate for an amount of radiation directed towards the portion of the photoresist so as to expose the portion of the photoresist to a target dosage of radiation.

公开(公告)号：US20180173090A1

公开(公告)日：2018-06-21

申请号：US15653784

申请日：2017-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chun Wang ,  Chi-Ping Liu ,  Feng-Ju Chang ,  Ching-Hsu Chang ,  Wen Hao Liu ,  Chia-Feng Yeh ,  Ming-Hui Chih ,  Cheng Kun Tsai ,  Wei-Chen Chien ,  Wen-Chun Huang ,  Yu-Po Tang

IPC: G03F1/36 ,  G06F17/50

CPC classification number: G03F1/36 ,  G06F17/5081

Abstract: Optical proximity correction (OPC) based computational lithography techniques are disclosed herein for enhancing lithography printability. An exemplary mask optimization method includes receiving an integrated circuit (IC) design layout having an IC pattern; generating target points for a contour corresponding with the IC pattern based on a target placement model, wherein the target placement model is selected based on a classification of the IC pattern; and performing an OPC on the IC pattern using the target points, thereby generating a modified IC design layout. The method can further include fabricating a mask based on the modified IC design layout. The OPC can select an OPC model based on the classification of the IC pattern. The OPC model can weight the target placement model.

公开(公告)号：US11308256B2

公开(公告)日：2022-04-19

申请号：US16907767

申请日：2020-06-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Chun Wang ,  Cheng Kun Tsai ,  Wen-Chun Huang ,  Wei-Chen Chien ,  Chi-Ping Liu

IPC: G06F7/50 ,  G06F30/398 ,  G03F1/36 ,  G06F30/20

Abstract: Implementations of the disclosure provide a method of fabricating an integrated circuit (IC). The method includes receiving an IC design layout; performing optical proximity correction (OPC) process to the IC design layout to produce a corrected IC design layout; and verifying the corrected IC design layout using a machine learning algorithm. The post OPC verification includes using the machine learning algorithm to identify one or more features of the corrected IC design layout; comparing the one or more identified features to a database comprising a plurality of features; and verifying the corrected IC design layout based on labels in the database associated with the plurality of features.

公开(公告)号：US10527928B2

公开(公告)日：2020-01-07

申请号：US15653784

申请日：2017-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chun Wang ,  Chi-Ping Liu ,  Feng-Ju Chang ,  Ching-Hsu Chang ,  Wen Hao Liu ,  Chia-Feng Yeh ,  Ming-Hui Chih ,  Cheng Kun Tsai ,  Wei-Chen Chien ,  Wen-Chun Huang ,  Yu-Po Tang

IPC: G06F17/50 ,  G03F1/36

Abstract: Optical proximity correction (OPC) based computational lithography techniques are disclosed herein for enhancing lithography printability. An exemplary mask optimization method includes receiving an integrated circuit (IC) design layout having an IC pattern; generating target points for a contour corresponding with the IC pattern based on a target placement model, wherein the target placement model is selected based on a classification of the IC pattern; and performing an OPC on the IC pattern using the target points, thereby generating a modified IC design layout. The method can further include fabricating a mask based on the modified IC design layout. The OPC can select an OPC model based on the classification of the IC pattern. The OPC model can weight the target placement model.

公开(公告)号：US20190147134A1

公开(公告)日：2019-05-16

申请号：US15812826

申请日：2017-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chun Wang ,  Cheng Kun Tsai ,  Wen-Chun Huang ,  Wei-Chen Chien ,  Chi-Ping Liu

IPC: G06F17/50 ,  G03F1/36

Abstract: Implementations of the disclosure provide a method of fabricating an integrated circuit (IC). The method includes receiving an IC design layout; performing optical proximity correction (OPC) process to the IC design layout to produce a corrected IC design layout; and verifying the corrected IC design layout using a machine learning algorithm. The post OPC verification includes using the machine learning algorithm to identify one or more features of the corrected IC design layout; comparing the one or more identified features to a database comprising a plurality of features; and verifying the corrected IC design layout based on labels in the database associated with the plurality of features.

公开(公告)号：US11048161B2

公开(公告)日：2021-06-29

申请号：US16727994

申请日：2019-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chun Wang ,  Chi-Ping Liu ,  Feng-Ju Chang ,  Ching-Hsu Chang ,  Wen Hao Liu ,  Chia-Feng Yeh ,  Ming-Hui Chih ,  Cheng Kun Tsai ,  Wei-Chen Chien ,  Wen-Chun Huang ,  Yu-Po Tang

IPC: G03F1/36 ,  G06F30/398

Abstract: Optical proximity correction (OPC) based computational lithography techniques are disclosed herein for enhancing lithography printability. An exemplary mask optimization method includes receiving an integrated circuit (IC) design layout having an IC pattern; generating target points for a contour corresponding with the IC pattern based on a target placement model, wherein the target placement model is selected based on a classification of the IC pattern; and performing an OPC on the IC pattern using the target points, thereby generating a modified IC design layout. The method can further include fabricating a mask based on the modified IC design layout. The OPC can select an OPC model based on the classification of the IC pattern. The OPC model can weight the target placement model.

公开(公告)号：US10691864B2

公开(公告)日：2020-06-23

申请号：US15812826

申请日：2017-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chun Wang ,  Cheng Kun Tsai ,  Wen-Chun Huang ,  Wei-Chen Chien ,  Chi-Ping Liu

IPC: G06F17/50 ,  G06F30/398 ,  G03F1/36 ,  G06F30/20

Abstract: Implementations of the disclosure provide a method of fabricating an integrated circuit (IC). The method includes receiving an IC design layout; performing optical proximity correction (OPC) process to the IC design layout to produce a corrected IC design layout; and verifying the corrected IC design layout using a machine learning algorithm. The post OPC verification includes using the machine learning algorithm to identify one or more features of the corrected IC design layout; comparing the one or more identified features to a database comprising a plurality of features; and verifying the corrected IC design layout based on labels in the database associated with the plurality of features.

公开(公告)号：US10520829B2

公开(公告)日：2019-12-31

申请号：US15715943

申请日：2017-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chun Wang ,  Chi-Ping Liu ,  Cheng Kun Tsai ,  Wei-Chen Chien ,  Wen-Chun Huang

IPC: G06F17/50 ,  G03F7/20

Abstract: Examples of optical proximity correction (OPC) based computational lithography techniques are disclosed herein. An exemplary method includes receiving an IC design layout that includes an IC feature, the IC feature specifying a mask feature for selectively exposing to radiation a portion of a photoresist disposed on a substrate; determining topographical information of an underlying layer disposed on the substrate between the photoresist and the substrate; performing an OPC process on the IC feature to generate a modified IC feature; and providing a modified IC design layout including the modified IC feature for fabricating a mask based on the modified IC design layout. The OPC process may use the topographical information of the underlying layer to compensate for an amount of radiation directed towards the portion of the photoresist so as to expose the portion of the photoresist to a target dosage of radiation.