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    Methodology for pattern correction
    2.
    发明授权
    Methodology for pattern correction 有权
    模式校正方法

    公开(公告)号：US09026955B1

    公开(公告)日：2015-05-05

    申请号：US14051568

    申请日：2013-10-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hung-Chun Wang ,  Ming-Hui Chih ,  Ping-Chieh Wu ,  Chun-Hung Wu ,  Feng-Ju Chang ,  Cheng-Kun Tsai ,  Wen-Chun Huang ,  Ru-Gun Liu

    IPC: G06F17/50

    CPC classification number: G03F1/36 ,  G03F7/70433 ,  H01L21/3212 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present disclosure relates to a method of integrated chip (IC) design pattern correction that reduces pattern correction cycle time by separately correcting main feature shapes and dummy shapes of the IC design, and an associated apparatus. In some embodiments, the method is performed by forming an IC design having a plurality of main feature shapes. A plurality of dummy shapes are added to the IC design to improve a process window of the IC design. The plurality of main feature shapes are corrected using a first pattern correction process. One or more of the plurality of dummy shapes are subsequently corrected using a second pattern correction process separate from the first pattern correction process. By separately correcting dummy shapes and main feature shapes, the dummy shapes can be subjected to a different pattern correction process having lower time/resource demands, thereby reducing the pattern correction cycle time.

    Abstract translation: 本公开涉及通过分开校正IC设计的主要特征形状和虚拟形状以及相关联的装置来减少图案校正周期时间的集成芯片（IC）设计图案校正的方法。 在一些实施例中，通过形成具有多个主要特征形状的IC设计来执行该方法。 将多个虚拟形状添加到IC设计中以改善IC设计的处理窗口。 使用第一图案校正处理来校正多个主要特征形状。 随后使用与第一图案校正处理分开的第二图案校正处理来校正多个虚拟形状中的一个或多个。 通过单独地校正虚拟形状和主要特征形状，可以对虚拟形状进行具有较低时间/资源需求的不同的图案校正处理，从而减少图案校正周期时间。

    Layout Design for Electron-Beam High Volume Manufacturing
    3.
    发明申请
    Layout Design for Electron-Beam High Volume Manufacturing 有权
    电子束大批量制造的布局设计

    公开(公告)号：US20140115546A1

    公开(公告)日：2014-04-24

    申请号：US13657992

    申请日：2012-10-23

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.

    Inventor： Hung-Chun Wang ,  Shao-Yun Fang ,  Tzu-Chin Lin ,  Wen-Chun Huang ,  Ru-Gun Liu

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5068 ,  G06F2217/06 ,  G06F2217/12 ,  Y02P90/265

    Abstract: The present disclosure relates to a method and apparatus to create a physical layout for electron-beam lithography, comprising defining a layout grid for a physical design, the layout grid further comprising vertical grid lines which coincide with stitching lines resulting from partitioning the physical design into a plurality of subfields. The physical design is assembled in accordance with design restrictions regarding interaction between design shapes and the layout grid. In some embodiments, the design restrictions are realized though layout restrictions. In some embodiments, the design restrictions are realized by shifting standard cells to minimize design shape interaction with the layout grid in a post-layout step. In some embodiments, the design restrictions are realized by exchanging positions between a plurality of standard cells for an exchange permutation which minimizes the number of interactions in a post-layout step. In some embodiments a routing grid is refined to rule out interactions between a subset of design constructs and the layout grid. Remaining design shape placement is then optimized along the routing grid relative to the stitching lines.

    Abstract translation: 本公开涉及一种用于创建用于电子束光刻的物理布局的方法和装置，包括定义用于物理设计的布局网格，所述布局网格还包括垂直网格线，其与由物理设计分割所产生的缝合线重合 多个子场。 物理设计根据设计形状和布局网格之间相互作用的设计限制进行组装。 在一些实施例中，通过布局限制来实现设计限制。 在一些实施例中，通过移动标准单元以在后布局步骤中最小化与布局格栅的设计形状交互来实现设计限制。 在一些实施例中，通过交换多个标准单元之间的位置来实现设计限制，用于交换置换，其最小化后布局步骤中的交互次数。 在一些实施例中，路由网格被改进以排除设计构造的子集与布局网格之间的交互。 然后沿着布线网格相对于缝合线优化剩余的设计形状布局。

    Optical Proximity Correction Methodology Using Underlying Layer Information
    4.
    发明申请
    Optical Proximity Correction Methodology Using Underlying Layer Information 审中-公开

    公开(公告)号：US20190094710A1

    公开(公告)日：2019-03-28

    申请号：US15715943

    申请日：2017-09-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hung-Chun Wang ,  Chi-Ping Liu ,  Cheng Kun Tsai ,  Wei-Chen Chien ,  Wen-Chun Huang

    IPC: G03F7/20 ,  G06F17/50

    Abstract: Examples of optical proximity correction (OPC) based computational lithography techniques are disclosed herein. An exemplary method includes receiving an IC design layout that includes an IC feature, the IC feature specifying a mask feature for selectively exposing to radiation a portion of a photoresist disposed on a substrate; determining topographical information of an underlying layer disposed on the substrate between the photoresist and the substrate; performing an OPC process on the IC feature to generate a modified IC feature; and providing a modified IC design layout including the modified IC feature for fabricating a mask based on the modified IC design layout. The OPC process may use the topographical information of the underlying layer to compensate for an amount of radiation directed towards the portion of the photoresist so as to expose the portion of the photoresist to a target dosage of radiation.

    METHODOLOGY FOR PATTERN DENSITY OPTIMIZATION
    6.
    发明申请
    METHODOLOGY FOR PATTERN DENSITY OPTIMIZATION 审中-公开
    模式密度优化方法

    公开(公告)号：US20160275232A1

    公开(公告)日：2016-09-22

    申请号：US15170026

    申请日：2016-06-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hung-Chun Wang ,  Ming-Hui Chih ,  Ping-Chieh Wu ,  Chun-Hung Wu ,  Wen-Hao Liu ,  Cheng-Hsuan Huang ,  Cheng-Kun Tsai ,  Wen-Chun Huang ,  Ru-Gun Liu

    IPC: G06F17/50 ,  G03F1/36

    CPC classification number: G06F17/5081 ,  G03F1/36

    Abstract: The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by performing an initial data preparation process on an IC design including a graphical representation of a layout used to fabricate an integrated chip. The initial data preparation process is performed by using a data preparation element to generate a modified IC design having modified shapes that are modified forms of shapes within the IC design. One or more low-pattern-density areas of the modified IC design are identified using a local density checking element. One or more dummy shapes are added within the one or more low-pattern-density areas using a dummy shape insertion element. The one or more dummy shapes are separated from the modified shapes by a non-zero space.

    Abstract translation: 本公开涉及一种利用低OPC（光学邻近校正）周期时间改进图案密度的方法，以及相关联的装置。 在一些实施例中，通过对包括用于制造集成芯片的布局的图形表示的IC设计执行初始数据准备处理来执行该方法。 通过使用数据准备元件来进行初始数据准备处理，以生成具有改进形状的修改的IC设计，其是IC设计中的形状的修改形式。 使用局部密度检查元件来识别修改的IC设计的一个或多个低图案密度区域。 使用虚拟形状插入元件在一个或多个低图案密度区域内添加一个或多个虚拟形状。 一个或多个虚拟形状通过非零空间与修改后的形状分离。

    Layout design for electron-beam high volume manufacturing
    7.
    发明授权
    Layout design for electron-beam high volume manufacturing 有权
    电子束大批量制造布局设计

    公开(公告)号：US08949749B2

    公开(公告)日：2015-02-03

    申请号：US13657992

    申请日：2012-10-23

    Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

    Inventor： Hung-Chun Wang ,  Shao-Yun Fang ,  Tzu-Chin Lin ,  Wen-Chun Huang ,  Ru-Gun Liu

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5068 ,  G06F2217/06 ,  G06F2217/12 ,  Y02P90/265

    Abstract: The present disclosure relates to a method and apparatus to create a physical layout for electron-beam lithography, comprising defining a layout grid for a physical design, the layout grid further comprising vertical grid lines which coincide with stitching lines resulting from partitioning the physical design into a plurality of subfields. The physical design is assembled in accordance with design restrictions regarding interaction between design shapes and the layout grid. In some embodiments, the design restrictions are realized though layout restrictions. In some embodiments, the design restrictions are realized by shifting standard cells to minimize design shape interaction with the layout grid in a post-layout step. In some embodiments, the design restrictions are realized by exchanging positions between a plurality of standard cells for an exchange permutation which minimizes the number of interactions in a post-layout step. In some embodiments a routing grid is refined to rule out interactions between a subset of design constructs and the layout grid. Remaining design shape placement is then optimized along the routing grid relative to the stitching lines.

    Abstract translation: 本公开涉及一种用于创建用于电子束光刻的物理布局的方法和装置，包括定义用于物理设计的布局网格，所述布局网格还包括垂直网格线，其与由物理设计分割所产生的缝合线重合 多个子场。 物理设计根据设计形状和布局网格之间相互作用的设计限制进行组装。 在一些实施例中，通过布局限制来实现设计限制。 在一些实施例中，通过移动标准单元以在后布局步骤中最小化与布局格栅的设计形状交互来实现设计限制。 在一些实施例中，通过交换多个标准单元之间的位置来实现设计限制，用于交换置换，其最小化后布局步骤中的交互次数。 在一些实施例中，路由网格被改进以排除设计构造的子集与布局网格之间的交互。 然后沿着布线网格相对于缝合线优化剩余的设计形状布局。

    Methodology for pattern density optimization
    8.
    发明授权
    Methodology for pattern density optimization 有权
    模式密度优化方法

    公开(公告)号：US09411924B2

    公开(公告)日：2016-08-09

    申请号：US14051549

    申请日：2013-10-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hung-Chun Wang ,  Ming-Hui Chih ,  Ping-Chieh Wu ,  Chun-Hung Wu ,  Wen-Hao Liu ,  Cheng-Hsuan Huang ,  Cheng-Kun Tsai ,  Wen-Chun Huang ,  Ru-Gun Liu

    IPC: G06F17/50 ,  G03F1/36

    CPC classification number: G06F17/5081 ,  G03F1/36

    Abstract: The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by forming an integrated chip (IC) design that is a graphical representation of an integrated chip. One or more low-pattern-density areas of the IC design are identified having a pattern density that results in a processing failure. The low-pattern-density areas are a subset of the IC design. The pattern density is adjusted within the low-pattern-density area by adding one or more dummy shapes within the low-pattern-density areas. A data preparation process is then performed on the IC design to modify shapes of the one or more dummy shapes within the low-pattern-density areas. By introducing dummy shapes into a local area, rather than into an entire integrated chip design, the demands of the subsequent data preparation process are reduced.

    Abstract translation: 本公开涉及一种利用低OPC（光学邻近校正）周期时间改进图案密度的方法，以及相关联的装置。 在一些实施例中，该方法通过形成作为集成芯片的图形表示的集成芯片（IC）设计来执行。 识别IC设计中的一个或多个低图案密度区域具有导致处理失败的图案密度。 低图案密度区域是IC设计的一个子集。 通过在低图案密度区域内添加一个或多个虚拟形状，在低图案密度区域内调整图案密度。 然后对IC设计执行数据准备处理，以修改低图案密度区域内的一个或多个虚拟形状的形状。 通过将虚拟形状引入局部区域而不是整个集成芯片设计中，随后的数据准备过程的需求减少。

    Layout design for electron-beam high volume manufacturing
    9.
    发明授权
    Layout design for electron-beam high volume manufacturing 有权

    公开(公告)号：US09165106B2

    公开(公告)日：2015-10-20

    申请号：US14611331

    申请日：2015-02-02

    Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

    Inventor： Hung-Chun Wang ,  Shao-Yun Fang ,  Tzu-Chin Lin ,  Wen-Chun Huang ,  Ru-Gun Liu

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5068 ,  G06F2217/06 ,  G06F2217/12 ,  Y02P90/265

    Abstract: The present disclosure relates to a method and apparatus to create a physical layout for electron-beam lithography, comprising defining a layout grid for a physical design, the layout grid further comprising vertical grid lines which coincide with stitching lines resulting from partitioning the physical design into a plurality of subfields. The physical design is assembled in accordance with design restrictions regarding interaction between design shapes and the layout grid. In some embodiments, the design restrictions are realized though layout restrictions. In some embodiments, the design restrictions are realized by shifting standard cells to minimize design shape interaction with the layout grid in a post-layout step. In some embodiments, the design restrictions are realized by exchanging positions between a plurality of standard cells for an exchange permutation which minimizes the number of interactions in a post-layout step. In some embodiments a routing grid is refined to rule out interactions between a subset of design constructs and the layout grid. Remaining design shape placement is then optimized along the routing grid relative to the stitching lines.

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