公开(公告)号：US10527928B2

公开(公告)日：2020-01-07

申请号：US15653784

申请日：2017-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chun Wang ,  Chi-Ping Liu ,  Feng-Ju Chang ,  Ching-Hsu Chang ,  Wen Hao Liu ,  Chia-Feng Yeh ,  Ming-Hui Chih ,  Cheng Kun Tsai ,  Wei-Chen Chien ,  Wen-Chun Huang ,  Yu-Po Tang

IPC: G06F17/50 ,  G03F1/36

Abstract: Optical proximity correction (OPC) based computational lithography techniques are disclosed herein for enhancing lithography printability. An exemplary mask optimization method includes receiving an integrated circuit (IC) design layout having an IC pattern; generating target points for a contour corresponding with the IC pattern based on a target placement model, wherein the target placement model is selected based on a classification of the IC pattern; and performing an OPC on the IC pattern using the target points, thereby generating a modified IC design layout. The method can further include fabricating a mask based on the modified IC design layout. The OPC can select an OPC model based on the classification of the IC pattern. The OPC model can weight the target placement model.

公开(公告)号：US20180173090A1

公开(公告)日：2018-06-21

申请号：US15653784

申请日：2017-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chun Wang ,  Chi-Ping Liu ,  Feng-Ju Chang ,  Ching-Hsu Chang ,  Wen Hao Liu ,  Chia-Feng Yeh ,  Ming-Hui Chih ,  Cheng Kun Tsai ,  Wei-Chen Chien ,  Wen-Chun Huang ,  Yu-Po Tang

IPC: G03F1/36 ,  G06F17/50

CPC classification number: G03F1/36 ,  G06F17/5081

Abstract: Optical proximity correction (OPC) based computational lithography techniques are disclosed herein for enhancing lithography printability. An exemplary mask optimization method includes receiving an integrated circuit (IC) design layout having an IC pattern; generating target points for a contour corresponding with the IC pattern based on a target placement model, wherein the target placement model is selected based on a classification of the IC pattern; and performing an OPC on the IC pattern using the target points, thereby generating a modified IC design layout. The method can further include fabricating a mask based on the modified IC design layout. The OPC can select an OPC model based on the classification of the IC pattern. The OPC model can weight the target placement model.

公开(公告)号：US09026955B1

公开(公告)日：2015-05-05

申请号：US14051568

申请日：2013-10-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chun Wang ,  Ming-Hui Chih ,  Ping-Chieh Wu ,  Chun-Hung Wu ,  Feng-Ju Chang ,  Cheng-Kun Tsai ,  Wen-Chun Huang ,  Ru-Gun Liu

IPC: G06F17/50

CPC classification number: G03F1/36 ,  G03F7/70433 ,  H01L21/3212 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a method of integrated chip (IC) design pattern correction that reduces pattern correction cycle time by separately correcting main feature shapes and dummy shapes of the IC design, and an associated apparatus. In some embodiments, the method is performed by forming an IC design having a plurality of main feature shapes. A plurality of dummy shapes are added to the IC design to improve a process window of the IC design. The plurality of main feature shapes are corrected using a first pattern correction process. One or more of the plurality of dummy shapes are subsequently corrected using a second pattern correction process separate from the first pattern correction process. By separately correcting dummy shapes and main feature shapes, the dummy shapes can be subjected to a different pattern correction process having lower time/resource demands, thereby reducing the pattern correction cycle time.

Abstract translation: 本公开涉及通过分开校正IC设计的主要特征形状和虚拟形状以及相关联的装置来减少图案校正周期时间的集成芯片（IC）设计图案校正的方法。 在一些实施例中，通过形成具有多个主要特征形状的IC设计来执行该方法。 将多个虚拟形状添加到IC设计中以改善IC设计的处理窗口。 使用第一图案校正处理来校正多个主要特征形状。 随后使用与第一图案校正处理分开的第二图案校正处理来校正多个虚拟形状中的一个或多个。 通过单独地校正虚拟形状和主要特征形状，可以对虚拟形状进行具有较低时间/资源需求的不同的图案校正处理，从而减少图案校正周期时间。

公开(公告)号：US11048161B2

公开(公告)日：2021-06-29

申请号：US16727994

申请日：2019-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chun Wang ,  Chi-Ping Liu ,  Feng-Ju Chang ,  Ching-Hsu Chang ,  Wen Hao Liu ,  Chia-Feng Yeh ,  Ming-Hui Chih ,  Cheng Kun Tsai ,  Wei-Chen Chien ,  Wen-Chun Huang ,  Yu-Po Tang

IPC: G03F1/36 ,  G06F30/398

Abstract: Optical proximity correction (OPC) based computational lithography techniques are disclosed herein for enhancing lithography printability. An exemplary mask optimization method includes receiving an integrated circuit (IC) design layout having an IC pattern; generating target points for a contour corresponding with the IC pattern based on a target placement model, wherein the target placement model is selected based on a classification of the IC pattern; and performing an OPC on the IC pattern using the target points, thereby generating a modified IC design layout. The method can further include fabricating a mask based on the modified IC design layout. The OPC can select an OPC model based on the classification of the IC pattern. The OPC model can weight the target placement model.

公开(公告)号：US20150106773A1

公开(公告)日：2015-04-16

申请号：US14051568

申请日：2013-10-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chun Wang ,  Ming-Hui Chih ,  Ping-Chieh Wu ,  Chun-Hung Wu ,  Feng-Ju Chang ,  Cheng-Kun Tsai ,  Wen-Chun Huang ,  Ru-Gun Liu

IPC: G06F17/50

CPC classification number: G03F1/36 ,  G03F7/70433 ,  H01L21/3212 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a method of integrated chip (IC) design pattern correction that reduces pattern correction cycle time by separately correcting main feature shapes and dummy shapes of the IC design, and an associated apparatus. In some embodiments, the method is performed by forming an IC design having a plurality of main feature shapes. A plurality of dummy shapes are added to the IC design to improve a process window of the IC design. The plurality of main feature shapes are corrected using a first pattern correction process. One or more of the plurality of dummy shapes are subsequently corrected using a second pattern correction process separate from the first pattern correction process. By separately correcting dummy shapes and main feature shapes, the dummy shapes can be subjected to a different pattern correction process having lower time/resource demands, thereby reducing the pattern correction cycle time.

Abstract translation: 本公开涉及通过分开校正IC设计的主要特征形状和虚拟形状以及相关联的装置来减少图案校正周期时间的集成芯片（IC）设计图案校正的方法。 在一些实施例中，通过形成具有多个主要特征形状的IC设计来执行该方法。 将多个虚拟形状添加到IC设计中以改善IC设计的处理窗口。 使用第一图案校正处理来校正多个主要特征形状。 随后使用与第一图案校正处理分开的第二图案校正处理来校正多个虚拟形状中的一个或多个。 通过单独地校正虚拟形状和主要特征形状，可以对虚拟形状进行具有较低时间/资源需求的不同的图案校正处理，从而减少图案校正周期时间。