公开(公告)号：US12027628B2

公开(公告)日：2024-07-02

申请号：US18303924

申请日：2023-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Yan Chung ,  Chao-Ching Cheng ,  Chao-Hsin Chien

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/68 ,  H01L29/76

CPC classification number: H01L29/78645 ,  H01L21/02565 ,  H01L21/02568 ,  H01L21/0262 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/66484 ,  H01L29/66969 ,  H01L29/685 ,  H01L29/7606 ,  H01L29/78648 ,  H01L29/78681 ,  H01L29/7869 ,  H01L29/78696

Abstract: In an embodiment, a method includes forming a first gate electrode over a substrate. The method also includes forming a first gate dielectric layer over the first gate electrode. The method also includes depositing a semiconductor layer over the first gate dielectric layer. The method also includes forming source/drain regions over the first gate dielectric layer and the semiconductor layer, the source/drain regions overlapping ends of the semiconductor layer. The method also includes forming a second gate dielectric layer over the semiconductor layer and the source/drain regions. The method also includes and forming a second gate electrode over the second gate dielectric layer.

公开(公告)号：US20220165871A1

公开(公告)日：2022-05-26

申请号：US17324893

申请日：2021-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Yan Chung ,  Chao-Ching Cheng ,  Chao-Hsin Chien

IPC: H01L29/68 ,  H01L21/02 ,  H01L29/24 ,  H01L29/76 ,  H01L29/786 ,  H01L29/66

Abstract: In an embodiment, a method includes forming a first gate electrode over a substrate. The method also includes forming a first gate dielectric layer over the first gate electrode. The method also includes depositing a semiconductor layer over the first gate dielectric layer. The method also includes forming source/drain regions over the first gate dielectric layer and the semiconductor layer, the source/drain regions overlapping ends of the semiconductor layer. The method also includes forming a second gate dielectric layer over the semiconductor layer and the source/drain regions. The method also includes and forming a second gate electrode over the second gate dielectric layer.

公开(公告)号：US20230253503A1

公开(公告)日：2023-08-10

申请号：US18303924

申请日：2023-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Yan Chung ,  Chao-Ching Cheng ,  Chao-Hsin Chien

IPC: H01L29/786 ,  H01L29/68 ,  H01L21/02 ,  H01L29/66 ,  H01L29/76 ,  H01L29/24 ,  H01L29/423

CPC classification number: H01L29/78645 ,  H01L29/685 ,  H01L21/02565 ,  H01L21/02568 ,  H01L21/0262 ,  H01L29/66969 ,  H01L29/7606 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696 ,  H01L29/24 ,  H01L29/42384

Abstract: In an embodiment, a method includes forming a first gate electrode over a substrate. The method also includes forming a first gate dielectric layer over the first gate electrode. The method also includes depositing a semiconductor layer over the first gate dielectric layer. The method also includes forming source/drain regions over the first gate dielectric layer and the semiconductor layer, the source/drain regions overlapping ends of the semiconductor layer. The method also includes forming a second gate dielectric layer over the semiconductor layer and the source/drain regions. The method also includes and forming a second gate electrode over the second gate dielectric layer.

公开(公告)号：US11670720B2

公开(公告)日：2023-06-06

申请号：US17324893

申请日：2021-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Yan Chung ,  Chao-Ching Cheng ,  Chao-Hsin Chien

IPC: H01L29/786 ,  H01L29/68 ,  H01L21/02 ,  H01L29/66 ,  H01L29/76 ,  H01L29/24 ,  H01L29/423

CPC classification number: H01L29/78645 ,  H01L21/0262 ,  H01L21/02565 ,  H01L21/02568 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/685 ,  H01L29/7606 ,  H01L29/7869 ,  H01L29/78648 ,  H01L29/78696

Abstract: In an embodiment, a method includes forming a first gate electrode over a substrate. The method also includes forming a first gate dielectric layer over the first gate electrode. The method also includes depositing a semiconductor layer over the first gate dielectric layer. The method also includes forming source/drain regions over the first gate dielectric layer and the semiconductor layer, the source/drain regions overlapping ends of the semiconductor layer. The method also includes forming a second gate dielectric layer over the semiconductor layer and the source/drain regions. The method also includes and forming a second gate electrode over the second gate dielectric layer.