公开(公告)号：US20200258899A1

公开(公告)日：2020-08-13

申请号：US16509728

申请日：2019-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chih Lai ,  Chung-Te Lin ,  Yung-Yu Chen

IPC: H01L27/11582 ,  H01L23/532

Abstract: Memory devices and methods of forming the same are provided. A memory device of the present disclosure includes a bottom dielectric layer, a gate structure extending vertically from the bottom dielectric layer, a stack structure, and a dielectric layer extending between the gate structure and the stack structure. The stack structure includes a first silicide layer, a second silicide layer, an oxide layer extending between the first and second silicide layers, a channel region over the oxide layer and extending between the first and second silicide layers, and an isolation layer over the second silicide layer. The first and second silicide layers include cobalt, titanium, tungsten, or palladium.

公开(公告)号：US20240099005A1

公开(公告)日：2024-03-21

申请号：US18524627

申请日：2023-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chih Lai ,  Chung-Te Lin ,  Yung-Yu Chen

IPC: H10B43/27 ,  H01L23/532 ,  H10B43/20

CPC classification number: H10B43/27 ,  H01L23/53257 ,  H10B43/20 ,  H01L29/40117

Abstract: Memory devices and methods of forming the same are provided. A memory device of the present disclosure includes a bottom dielectric layer, a gate structure extending vertically from the bottom dielectric layer, a stack structure, and a dielectric layer extending between the gate structure and the stack structure. The stack structure includes a first silicide layer, a second silicide layer, an oxide layer extending bet ween the first and second silicide layers, a channel region over the oxide layer and extending between the first and second silicide layers, and an isolation layer over the second silicide layer. The first and second silicide layers include cobalt, titanium, tungsten, or palladium.

公开(公告)号：US11856775B2

公开(公告)日：2023-12-26

申请号：US17228072

申请日：2021-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chih Lai ,  Chung-Te Lin ,  Yung-Yu Chen

IPC: H10B43/20 ,  H10B41/20 ,  H10B43/27 ,  H01L23/532 ,  H01L21/28

CPC classification number: H10B43/27 ,  H01L23/53257 ,  H10B43/20 ,  H01L29/40117 ,  H01L2924/1438

Abstract: Memory devices and methods of forming the same are provided. A memory device of the present disclosure includes a bottom dielectric layer, a gate structure extending vertically from the bottom dielectric layer, a stack structure, and a dielectric layer extending between the gate structure and the stack structure. The stack structure includes a first silicide layer, a second silicide layer, an oxide layer extending between the first and second silicide layers, a channel region over the oxide layer and extending between the first and second silicide layers, and an isolation layer over the second silicide layer. The first and second silicide layers include cobalt, titanium, tungsten, or palladium.

公开(公告)号：US20210233931A1

公开(公告)日：2021-07-29

申请号：US17228072

申请日：2021-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chih Lai ,  Chung-Te Lin ,  Yung-Yu Chen

IPC: H01L27/11582 ,  H01L23/532 ,  H01L27/11578

Abstract: Memory devices and methods of forming the same are provided. A memory device of the present disclosure includes a bottom dielectric layer, a gate structure extending vertically from the bottom dielectric layer, a stack structure, and a dielectric layer extending between the gate structure and the stack structure. The stack structure includes a first silicide layer, a second silicide layer, an oxide layer extending between the first and second silicide layers, a channel region over the oxide layer and extending between the first and second silicide layers, and an isolation layer over the second silicide layer. The first and second silicide layers include cobalt, titanium, tungsten, or palladium.

公开(公告)号：US10978473B2

公开(公告)日：2021-04-13

申请号：US16509728

申请日：2019-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chih Lai ,  Chung-Te Lin ,  Yung-Yu Chen

IPC: H01L27/11582 ,  H01L23/532 ,  H01L27/11578 ,  H01L21/28

Abstract: Memory devices and methods of forming the same are provided. A memory device of the present disclosure includes a bottom dielectric layer, a gate structure extending vertically from the bottom dielectric layer, a stack structure, and a dielectric layer extending between the gate structure and the stack structure. The stack structure includes a first silicide layer, a second silicide layer, an oxide layer extending between the first and second silicide layers, a channel region over the oxide layer and extending between the first and second silicide layers, and an isolation layer over the second silicide layer. The first and second silicide layers include cobalt, titanium, tungsten, or palladium.