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    FLASH MEMORY STRUCTURE AND METHOD OF FORMING THE SAME
    1.
    发明公开
    FLASH MEMORY STRUCTURE AND METHOD OF FORMING THE SAME 审中-公开

    公开(公告)号：US20240099005A1

    公开(公告)日：2024-03-21

    申请号：US18524627

    申请日：2023-11-30

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Sheng-Chih Lai ,  Chung-Te Lin ,  Yung-Yu Chen

    IPC分类号： H10B43/27 ,  H01L23/532 ,  H10B43/20

    CPC分类号： H10B43/27 ,  H01L23/53257 ,  H10B43/20 ,  H01L29/40117

    摘要： Memory devices and methods of forming the same are provided. A memory device of the present disclosure includes a bottom dielectric layer, a gate structure extending vertically from the bottom dielectric layer, a stack structure, and a dielectric layer extending between the gate structure and the stack structure. The stack structure includes a first silicide layer, a second silicide layer, an oxide layer extending bet ween the first and second silicide layers, a channel region over the oxide layer and extending between the first and second silicide layers, and an isolation layer over the second silicide layer. The first and second silicide layers include cobalt, titanium, tungsten, or palladium.

    Three-dimensional memory device and method
    2.
    发明授权
    Three-dimensional memory device and method 有权

    公开(公告)号：US11856781B2

    公开(公告)日：2023-12-26

    申请号：US17194715

    申请日：2021-03-08

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： TsuChing Yang ,  Hung-Chang Sun ,  Kuo Chang Chiang ,  Sheng-Chih Lai ,  Yu-Wei Jiang

    IPC分类号： H10B51/20 ,  H01L29/06 ,  H10B51/10

    CPC分类号： H10B51/20 ,  H01L29/0649 ,  H10B51/10

    摘要： A method of forming a three-dimensional (3D) memory device includes: forming, over a substrate, a layer stack having alternating layers of a first conductive material and a first dielectric material; forming trenches extending vertically through the layer stack from an upper surface of the layer stack distal from the substrate to a lower surface of the layer stack facing the substrate; lining sidewalls and bottoms of the trenches with a memory film; forming a channel material over the memory film, the channel material including an amorphous material; filling the trenches with a second dielectric material after forming the channel material; forming memory cell isolation regions in the second dielectric material; forming source lines (SLs) and bit lines (BLs) that extend vertically in the second dielectric material on opposing sides of the memory cell isolation regions; and crystallizing first portions of the channel material after forming the SLs and BLs.

    SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THEREOF
    5.
    发明申请
    SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THEREOF 有权

    公开(公告)号：US20220320119A1

    公开(公告)日：2022-10-06

    申请号：US17345499

    申请日：2021-06-11

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Yu-Wei Jiang ,  Sheng-Chih Lai ,  Feng-Cheng Yang ,  Chung-Te Lin

    IPC分类号： H01L27/1159 ,  H01L27/11587

    摘要： The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate and a stacked structure disposed on the substrate. The stacked structure includes multiple alternately stacked insulating layers and gate members. A core structure is disposed in the stacked structure. The core structure includes a memory layer, a channel member, a contact member, and a liner member. The channel member is disposed on the memory layer. The contact member is disposed on the channel member. The liner member surrounds a portion of the core structure. The present disclosure also provides a method for fabricating the semiconductor structure.

    3D ferroelectric memory
    6.
    发明授权
    3D ferroelectric memory 有权

    公开(公告)号：US11411025B2

    公开(公告)日：2022-08-09

    申请号：US16903545

    申请日：2020-06-17

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Sheng-Chih Lai ,  Chung-Te Lin

    IPC分类号： H01L21/00 ,  H01L27/11597 ,  H01L27/11592 ,  H01L27/1159 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28

    摘要： Various embodiments of the present disclosure are directed towards a metal-ferroelectric-insulator-semiconductor (MFIS) memory device, as well as a method for forming the MFIS memory device. According to some embodiments of the MFIS memory device, a lower source/drain region and an upper source/drain region are vertically stacked. A semiconductor channel overlies the lower source/drain region and underlies the upper source/drain region. The semiconductor channel extends from the lower source/drain region to the upper source/drain region. A control gate electrode extends along a sidewall of the semiconductor channel and further along individual sidewalls of the lower and upper source/drain regions. A gate dielectric layer and a ferroelectric layer separate the control gate electrode from the semiconductor channel and the lower and upper source/drain regions.

    MEMORY ARRAY CHANNEL REGIONS
    7.
    发明申请
    MEMORY ARRAY CHANNEL REGIONS 有权

    公开(公告)号：US20210375936A1

    公开(公告)日：2021-12-02

    申请号：US17150522

    申请日：2021-01-15

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Kuo-Chang Chiang ,  Hung-Chang Sun ,  Sheng-Chih Lai ,  TsuChing Yang ,  Yu-Wei Jiang

    IPC分类号： H01L27/11597 ,  H01L27/11587 ,  H01L29/786 ,  H01L27/1159 ,  G11C5/06

    摘要： A memory cell includes a ferroelectric (FE) material contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line. The OS layer comprises: a first region adjacent the FE material, the first region having a first concentration of a semiconductor element; a second region adjacent the source line, the second region having a second concentration of the semiconductor element; and a third region between the first region and the second region, the third region having a third concentration of the semiconductor element, the third concentration is greater than the second concentration and less than the first concentration.

    Method for fabricating memory device
    9.
    发明授权
    Method for fabricating memory device 有权

    公开(公告)号：US10971682B2

    公开(公告)日：2021-04-06

    申请号：US16866101

    申请日：2020-05-04

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    发明人： Tai-Yen Peng ,  Hui-Hsien Wei ,  Wei-Chih Wen ,  Pin-Ren Dai ,  Chien-Min Lee ,  Sheng-Chih Lai ,  Han-Ting Tsai ,  Chung-Te Lin

    IPC分类号： H01L43/12 ,  H01L27/22 ,  G11C11/16 ,  H01L43/08 ,  H01L43/02

    摘要： A method for fabricating a memory device is provided. The method includes depositing a resistance switching element layer over a bottom electrode layer; depositing a top electrode layer over the resistance switching element layer; etching the top electrode layer, the resistance switching element layer, and the bottom electrode layer to form a memory stack; depositing a first spacer layer over the memory stack and; etching the first spacer layer to form a first spacer extending along a sidewall of the memory stack; depositing a second spacer layer over the memory stack and the first spacer; etching the second spacer layer to form a second spacer extending along a sidewall of the first spacer; and depositing an etch stop layer over and in contact with a top of the second spacer, wherein the etch stop layer is spaced apart from the first spacer by a portion of the second spacer.