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    STATIC RANDOM ACCESS MEMORY WITH PRE-CHARGE CIRCUIT
    1.
    发明申请
    STATIC RANDOM ACCESS MEMORY WITH PRE-CHARGE CIRCUIT 有权

    公开(公告)号：US20220085035A1

    公开(公告)日：2022-03-17

    申请号：US17125688

    申请日：2020-12-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Po-Sheng WANG ,  Yangsyu LIN ,  Cheng Hung LEE

    IPC: H01L27/11 ,  G11C11/412 ,  G11C11/419

    Abstract: The present disclosure describes embodiments of a memory device with a pre-charge circuit. The memory device can include a memory cell, and the pre-charge circuit can include a first transistor and a second transistor. The first transistor includes a first gate terminal, a first source/drain (S/D) terminal coupled to a reference voltage, and a second S/D terminal coupled to a first terminal of the memory cell. The second transistor includes a second gate terminal, a third S/D terminal coupled to the reference voltage, and a fourth S/D terminal coupled to the second terminal of the memory cell. The first and second transistors are configured to pass the reference voltage in response to the control signal being applied to the first and second gate terminals, respectively.

    VOLTAGE SUPPLY SELECTION CIRCUIT
    6.
    发明申请
    VOLTAGE SUPPLY SELECTION CIRCUIT 有权

    公开(公告)号：US20230054498A1

    公开(公告)日：2023-02-23

    申请号：US17406273

    申请日：2021-08-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chia-Chen KUO ,  Yangsyu LIN ,  Yu-Hao HSU ,  Cheng Hung LEE ,  Hung-Jen LIAO ,  Jonathan Tsung-Yung CHANG

    IPC: H03K3/012

    Abstract: The present disclosure describes an example circuit for selecting a voltage supply. The circuit includes a first control switch, a first voltage supply switch, a second control switch, and a second voltage supply switch. The first control switch is configured to receive a control signal and a first voltage supply. The first voltage supply switch is electrically coupled to the first control switch and is configured to receive a second voltage supply. The second voltage supply switch is electrically coupled to the second control switch and configured to receive the first voltage supply. The first and second voltage supply switches are configured to selectively output the first and second voltage supplies based on the control signal.

    NEGATIVE BITLINE BOOST SCHEME FOR SRAM WRITE-ASSIST
    8.
    发明申请
    NEGATIVE BITLINE BOOST SCHEME FOR SRAM WRITE-ASSIST 审中-公开
    用于SRAM写协议的负号比特增强方案

    公开(公告)号：US20150262655A1

    公开(公告)日：2015-09-17

    申请号：US14727931

    申请日：2015-06-02

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Wei-Jer HSIEH ,  Yangsyu LIN ,  Hsiao Wen LU ,  Chiting CHENG ,  Jonathan Tsung-Yung CHANG

    IPC: G11C11/419

    CPC classification number: G11C11/419 ,  G11C7/12

    Abstract: A device includes a transistor switch coupled between a bit line voltage node and a ground node and a boost signal circuit coupled to a gate node of the transistor switch, where the boost signal circuit providing a boost signal responsive to a write enable signal. The device also includes a first delay element and a first capacitor in series with the first delay element. The first capacitor has a first end coupled to the bit line voltage node and a second end coupled to the gate node through the first delay element.

    Abstract translation: 一种器件包括耦合在位线电压节点和接地节点之间的晶体管开关和耦合到晶体管开关的栅极节点的升压信号电路，其中升压信号电路响应写使能信号而提供升压信号。 该装置还包括与第一延迟元件串联的第一延迟元件和第一电容器。 第一电容器具有耦合到位线电压节点的第一端和通过第一延迟元件耦合到栅极节点的第二端。

    HIGH DENSITY MEMORY STRUCTURE
    9.
    发明申请
    HIGH DENSITY MEMORY STRUCTURE 有权
    高密度存储器结构

    公开(公告)号：US20150121030A1

    公开(公告)日：2015-04-30

    申请号：US14068003

    申请日：2013-10-31

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yangsyu LIN ,  Hsiao Wen LU ,  Chiting CHENG ,  Jonathan Tsung-Yung CHANG

    IPC: G06F12/02

    CPC classification number: G11C11/419 ,  G11C7/18

    Abstract: A semiconductor memory comprises a plurality of sub banks each including one or more rows of memory bit cells connected to a set of local bit lines, wherein the sub banks share a same set of global bit lines for reading/writing data from/to the memory bit cells of the sub banks. The semiconductor memory chip further comprises a plurality of switch elements for each of the sub banks, wherein each of the switch elements connects the local bit line and the global bit line of a corresponding one of the memory bit cells in the sub bank for data transmission between the local bit line and the global bit line. The semiconductor memory chip further comprises a plurality of bank selection signal lines each connected to the switch elements in a corresponding one of the sub banks, wherein the bank selection signal lines carry a plurality of bank selection signals to select one of the sub banks for data transmission between the local bit lines and the global bit lines.

    Abstract translation: 半导体存储器包括多个子存储体，每个子存储体包括连接到一组局部位线的一行或多行存储器位单元，其中子存储体共享用于从/向存储器读/写数据的全局位线集合 子库的位单元。 半导体存储器芯片还包括用于每个子存储体的多个开关元件，其中每个开关元件连接子库中对应的一个存储单元的局部位线和全局位线，用于数据传输 在本地位线和全局位线之间。 半导体存储器芯片还包括多个存储体选择信号线，每条存储体选择信号线连接到相应的一个子存储体中的开关元件，其中存储体选择信号线传送多个存储体选择信号以选择一个子存储体用于数据 局部位线与全局位线之间的传输。

    LEAKAGE PATHWAY PREVENTION IN A MEMORY STORAGE DEVICE
    10.
    发明申请
    LEAKAGE PATHWAY PREVENTION IN A MEMORY STORAGE DEVICE 审中-公开

    公开(公告)号：US20200005835A1

    公开(公告)日：2020-01-02

    申请号：US16263904

    申请日：2019-01-31

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shang-Chi WU ,  Cheng Hung LEE ,  Chien-Kuo SU ,  Chiting CHENG ,  Yu-Hao HSU ,  Yangsyu LIN

    IPC: G11C7/10 ,  G11C7/12

    Abstract: The present disclosure describes various exemplary memory storage devices that can be programmed to write electronic data into one or more memory cells in a write mode of operation and/or to read the electronic data from the one or more memory cells in a read mode of operation. The various exemplary memory storage devices can select various control lines to read the electronic data from the one or more memory cells onto data lines and/or to write the electronic data from these data lines into the one or more memory cells. In some situations, these data lines are charged, also referred to as pre-charged, to a first logical value, such as a logical one, before the various exemplary memory storage devices write the electronic data into the one or more memory cells. During this pre-charging of these data lines, the various exemplary memory storage devices electrically isolate these data lines from specialized circuitry within these exemplary memory storage devices. This specialized circuitry, also referred to as a write driver, writes the electronic data onto these data lines for storage in the one or more memory cells during the write mode of operation.

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