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    LEAKAGE PATHWAY PREVENTION IN A MEMORY STORAGE DEVICE
    2.
    发明申请
    LEAKAGE PATHWAY PREVENTION IN A MEMORY STORAGE DEVICE 审中-公开

    公开(公告)号：US20200005835A1

    公开(公告)日：2020-01-02

    申请号：US16263904

    申请日：2019-01-31

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shang-Chi WU ,  Cheng Hung LEE ,  Chien-Kuo SU ,  Chiting CHENG ,  Yu-Hao HSU ,  Yangsyu LIN

    IPC: G11C7/10 ,  G11C7/12

    Abstract: The present disclosure describes various exemplary memory storage devices that can be programmed to write electronic data into one or more memory cells in a write mode of operation and/or to read the electronic data from the one or more memory cells in a read mode of operation. The various exemplary memory storage devices can select various control lines to read the electronic data from the one or more memory cells onto data lines and/or to write the electronic data from these data lines into the one or more memory cells. In some situations, these data lines are charged, also referred to as pre-charged, to a first logical value, such as a logical one, before the various exemplary memory storage devices write the electronic data into the one or more memory cells. During this pre-charging of these data lines, the various exemplary memory storage devices electrically isolate these data lines from specialized circuitry within these exemplary memory storage devices. This specialized circuitry, also referred to as a write driver, writes the electronic data onto these data lines for storage in the one or more memory cells during the write mode of operation.

    WORDLINE DOUBLER
    3.
    发明申请
    WORDLINE DOUBLER 有权

    公开(公告)号：US20140269141A1

    公开(公告)日：2014-09-18

    申请号：US13904653

    申请日：2013-05-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Hao HSU ,  Ming-Chien TSAI ,  Chen-Lin YANG

    IPC: G11C8/08

    CPC classification number: G11C8/08 ,  G11C7/06 ,  G11C7/12 ,  G11C11/419 ,  G11C29/50 ,  G11C29/52

    Abstract: A memory includes a clock generator for providing a first clock signal responsive to a second clock signal and a feedback signal. A feedback loop provides the feedback signal and includes a tracking wordline, a tracking bitline, a tracking bit cell, and a tracking wordline driver for driving the tracking wordline responsive to the first clock signal. The memory includes a tracking wordline level tuner for reducing a voltage level of a tracking wordline signal on the tracking wordline responsive to a weak bit control signal.

    Abstract translation: 存储器包括响应于第二时钟信号和反馈信号提供第一时钟信号的时钟发生器。 反馈回路提供反馈信号，并且包括跟踪字线，跟踪位线，跟踪位单元和用于响应于第一时钟信号驱动跟踪字线的跟踪字线驱动器。 存储器包括跟踪字线电平调谐器，用于响应弱位控制信号减小跟踪字线上的跟踪字线信号的电压电平。

    VOLTAGE SUPPLY SELECTION CIRCUIT
    4.
    发明申请
    VOLTAGE SUPPLY SELECTION CIRCUIT 有权

    公开(公告)号：US20230054498A1

    公开(公告)日：2023-02-23

    申请号：US17406273

    申请日：2021-08-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chia-Chen KUO ,  Yangsyu LIN ,  Yu-Hao HSU ,  Cheng Hung LEE ,  Hung-Jen LIAO ,  Jonathan Tsung-Yung CHANG

    IPC: H03K3/012

    Abstract: The present disclosure describes an example circuit for selecting a voltage supply. The circuit includes a first control switch, a first voltage supply switch, a second control switch, and a second voltage supply switch. The first control switch is configured to receive a control signal and a first voltage supply. The first voltage supply switch is electrically coupled to the first control switch and is configured to receive a second voltage supply. The second voltage supply switch is electrically coupled to the second control switch and configured to receive the first voltage supply. The first and second voltage supply switches are configured to selectively output the first and second voltage supplies based on the control signal.

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