WORDLINE DOUBLER
    3.
    发明申请

    公开(公告)号:US20140269141A1

    公开(公告)日:2014-09-18

    申请号:US13904653

    申请日:2013-05-29

    Abstract: A memory includes a clock generator for providing a first clock signal responsive to a second clock signal and a feedback signal. A feedback loop provides the feedback signal and includes a tracking wordline, a tracking bitline, a tracking bit cell, and a tracking wordline driver for driving the tracking wordline responsive to the first clock signal. The memory includes a tracking wordline level tuner for reducing a voltage level of a tracking wordline signal on the tracking wordline responsive to a weak bit control signal.

    Abstract translation: 存储器包括响应于第二时钟信号和反馈信号提供第一时钟信号的时钟发生器。 反馈回路提供反馈信号,并且包括跟踪字线,跟踪位线,跟踪位单元和用于响应于第一时钟信号驱动跟踪字线的跟踪字线驱动器。 存储器包括跟踪字线电平调谐器,用于响应弱位控制信号减小跟踪字线上的跟踪字线信号的电压电平。

Patent Agency Ranking