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    NEGATIVE BITLINE BOOST SCHEME FOR SRAM WRITE-ASSIST
    4.
    发明申请
    NEGATIVE BITLINE BOOST SCHEME FOR SRAM WRITE-ASSIST 审中-公开
    用于SRAM写协议的负号比特增强方案

    公开(公告)号：US20150262655A1

    公开(公告)日：2015-09-17

    申请号：US14727931

    申请日：2015-06-02

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Wei-Jer HSIEH ,  Yangsyu LIN ,  Hsiao Wen LU ,  Chiting CHENG ,  Jonathan Tsung-Yung CHANG

    IPC: G11C11/419

    CPC classification number: G11C11/419 ,  G11C7/12

    Abstract: A device includes a transistor switch coupled between a bit line voltage node and a ground node and a boost signal circuit coupled to a gate node of the transistor switch, where the boost signal circuit providing a boost signal responsive to a write enable signal. The device also includes a first delay element and a first capacitor in series with the first delay element. The first capacitor has a first end coupled to the bit line voltage node and a second end coupled to the gate node through the first delay element.

    Abstract translation: 一种器件包括耦合在位线电压节点和接地节点之间的晶体管开关和耦合到晶体管开关的栅极节点的升压信号电路，其中升压信号电路响应写使能信号而提供升压信号。 该装置还包括与第一延迟元件串联的第一延迟元件和第一电容器。 第一电容器具有耦合到位线电压节点的第一端和通过第一延迟元件耦合到栅极节点的第二端。

    HIGH DENSITY MEMORY STRUCTURE
    5.
    发明申请
    HIGH DENSITY MEMORY STRUCTURE 有权
    高密度存储器结构

    公开(公告)号：US20150121030A1

    公开(公告)日：2015-04-30

    申请号：US14068003

    申请日：2013-10-31

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yangsyu LIN ,  Hsiao Wen LU ,  Chiting CHENG ,  Jonathan Tsung-Yung CHANG

    IPC: G06F12/02

    CPC classification number: G11C11/419 ,  G11C7/18

    Abstract: A semiconductor memory comprises a plurality of sub banks each including one or more rows of memory bit cells connected to a set of local bit lines, wherein the sub banks share a same set of global bit lines for reading/writing data from/to the memory bit cells of the sub banks. The semiconductor memory chip further comprises a plurality of switch elements for each of the sub banks, wherein each of the switch elements connects the local bit line and the global bit line of a corresponding one of the memory bit cells in the sub bank for data transmission between the local bit line and the global bit line. The semiconductor memory chip further comprises a plurality of bank selection signal lines each connected to the switch elements in a corresponding one of the sub banks, wherein the bank selection signal lines carry a plurality of bank selection signals to select one of the sub banks for data transmission between the local bit lines and the global bit lines.

    Abstract translation: 半导体存储器包括多个子存储体，每个子存储体包括连接到一组局部位线的一行或多行存储器位单元，其中子存储体共享用于从/向存储器读/写数据的全局位线集合 子库的位单元。 半导体存储器芯片还包括用于每个子存储体的多个开关元件，其中每个开关元件连接子库中对应的一个存储单元的局部位线和全局位线，用于数据传输 在本地位线和全局位线之间。 半导体存储器芯片还包括多个存储体选择信号线，每条存储体选择信号线连接到相应的一个子存储体中的开关元件，其中存储体选择信号线传送多个存储体选择信号以选择一个子存储体用于数据 局部位线与全局位线之间的传输。

    LEVEL SHIFTER CIRCUIT USING BOOSTING CIRCUIT
    10.
    发明申请
    LEVEL SHIFTER CIRCUIT USING BOOSTING CIRCUIT 有权

    公开(公告)号：US20170264276A1

    公开(公告)日：2017-09-14

    申请号：US15065166

    申请日：2016-03-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Mahmut Sinangil ,  Hsin-Hsin KO ,  Chiting CHENG ,  Yen-Huei CHEN ,  Hung-Jen LIAO ,  Jonathan Tsung-Yung CHANG

    IPC: H03K3/356 ,  H03K19/0185

    CPC classification number: H03K3/356113 ,  H03K19/018521

    Abstract: A level shifter circuit is provided that uses a boosting circuit. The boosting circuit is configured to improve the operation of the level shifter circuit when the high voltages of voltage domains across the level shifter circuit are widely separated. A circuit apparatus includes a core level shifter circuit that changes a first voltage of an input signal to a second voltage of an output signal. The circuit apparatus further includes a first boosting circuit that is coupled to the core level shifter circuit and generates a first transient voltage applied to the core level shifter circuit when the input signal transitions from a low value to a high value. The circuit apparatus also includes a second boosting circuit that is coupled to the core level shifter circuit and generates a second transient voltage applied to the core level shifter circuit when the input signal transitions from a high value to a low value.

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