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    VOLTAGE SUPPLY SELECTION CIRCUIT
    2.
    发明申请
    VOLTAGE SUPPLY SELECTION CIRCUIT 有权

    公开(公告)号：US20230054498A1

    公开(公告)日：2023-02-23

    申请号：US17406273

    申请日：2021-08-19

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Chia-Chen KUO ,  Yangsyu LIN ,  Yu-Hao HSU ,  Cheng Hung LEE ,  Hung-Jen LIAO ,  Jonathan Tsung-Yung CHANG

    IPC分类号： H03K3/012

    摘要： The present disclosure describes an example circuit for selecting a voltage supply. The circuit includes a first control switch, a first voltage supply switch, a second control switch, and a second voltage supply switch. The first control switch is configured to receive a control signal and a first voltage supply. The first voltage supply switch is electrically coupled to the first control switch and is configured to receive a second voltage supply. The second voltage supply switch is electrically coupled to the second control switch and configured to receive the first voltage supply. The first and second voltage supply switches are configured to selectively output the first and second voltage supplies based on the control signal.

    SRAM CELL WORD LINE STRUCTURE WITH REDUCED RC EFFECTS
    4.
    发明申请
    SRAM CELL WORD LINE STRUCTURE WITH REDUCED RC EFFECTS 有权

    公开(公告)号：US20210265363A1

    公开(公告)日：2021-08-26

    申请号：US17320091

    申请日：2021-05-13

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    发明人： Hidehiro FUJIWARA ,  Wei-Min CHAN ,  Chih-Yu LIN ,  Yen-Huei CHEN ,  Hung-Jen LIAO

    IPC分类号： H01L27/11 ,  H01L27/02 ,  H01L21/321 ,  H01L21/768 ,  H01L23/528

    摘要： A device is disclosed that includes a fin structure disposed below a first metal layer, extending along a column direction, and corresponding to at least one transistor of a memory bit cell, a word line disposed in the first metal layer and extending along a row direction, a first metal island disposed in the first metal layer separated from the word line, and a first connection metal line disposed in a second metal layer above the first metal layer, extending along the column direction, and configured to couple a power supply through the first metal island to the fin structure. In a layout view, the first connection metal line is separated from the fin structure, and the fin structure crosses over the word line and the first metal island. A method is also disclosed herein.

    MEMORY CELL
    5.
    发明申请
    MEMORY CELL 审中-公开

    公开(公告)号：US20180151226A1

    公开(公告)日：2018-05-31

    申请号：US15799253

    申请日：2017-10-31

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Hidehiro FUJIWARA ,  Hung-Jen LIAO ,  Hsien-Yu PAN ,  Chih-Yu LIN ,  Yen-Huei CHEN ,  Chien-Chen LIN

    IPC分类号： G11C15/04 ,  H01L27/02

    摘要： A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.

    ANTENNA DIODE CIRCUIT
    7.
    发明申请
    ANTENNA DIODE CIRCUIT 有权

    公开(公告)号：US20220359496A1

    公开(公告)日：2022-11-10

    申请号：US17875108

    申请日：2022-07-27

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    发明人： Sahil Preet SINGH ,  Yen-Huei CHEN ,  Hung-Jen LIAO

    IPC分类号： H01L27/02 ,  H01L23/50 ,  H02H9/04

    摘要： A device includes a diode circuit. The diode circuit is coupled between a first input/output (I/O) pin and a second I/O pin of a circuit, and is configured to be turned off. The diode circuit is configured to provide a first discharging path for the first I/O pin of the circuit and a second discharging path for the second I/O pin of the circuit. The diode circuit includes a first transistor and a second transistor. The first transistor is between a node and the first I/O pin. The second transistor is between the node and the second I/O pin. The node is configured to receive a first voltage, and control terminals of the first transistor and the second transistor are configured to receive a second voltage. A voltage difference between the first voltage and the second voltage is configured to turn off the first transistor and the second transistor.

    MEMORY DEVICE WITH STRAP CELLS
    8.
    发明申请
    MEMORY DEVICE WITH STRAP CELLS 有权

    公开(公告)号：US20210217446A1

    公开(公告)日：2021-07-15

    申请号：US17214560

    申请日：2021-03-26

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    发明人： Jonathan Tsung-Yung CHANG ,  Cheng-Hung LEE ,  Chi-Ting CHENG ,  Hung-Jen LIAO ,  Jhon-Jhy LIAW ,  Yen-Huei CHEN

    IPC分类号： G11C5/02 ,  G11C5/14 ,  G11C7/10 ,  G11C7/12 ,  G11C11/417 ,  G11C7/22

    摘要： A device disclosed includes first and second rows of memory cells, a first data line, and a first continuous data line. The first and second rows of memory cells are arranged in a first sub-bank and a second sub-bank, separated from the first sub-bank, respectively. The first data line is arranged across the first sub-bank and coupled to a first memory cell in the first row of memory cells. The first continuous data line includes a first portion arranged across the first sub-bank and a second portion arranged across the second sub-bank. The first continuous data line is coupled to a second memory cell in the second row of memory cells. The first portion of the first continuous data line is disposed in a first metal layer. The first data line and the second portion of the first continuous data line are in a second metal layer.