公开(公告)号：US20200005837A1

公开(公告)日：2020-01-02

申请号：US16273527

申请日：2019-02-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Atul Katoch ,  Ali Taghvaei

IPC分类号： G11C7/12 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/419 ,  G11C7/06 ,  G11C7/18 ,  G11C16/04

摘要： A memory device Input/Output includes a memory cell having a local bit line. A first IO circuit is coupled to the local bit line and is configured to output a local IO signal to a global bit line. A second IO circuit is coupled to the global bit line and is configured to output a global IO signal. A latch circuit is configured to latch the local IO signal in response to a data signal on the local bit line.

公开(公告)号：US10163477B1

公开(公告)日：2018-12-25

申请号：US15656887

申请日：2017-07-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Sanjeev Kumar Jain ,  Ali Taghvaei ,  Atul Katoch

IPC分类号： G11C8/00 ,  G11C7/24 ,  G11C8/10

摘要： A memory array having a first port and a second port is disclosed. The memory array includes: a first memory cell, wherein access to the first memory cell through the first port is controlled by a first word line, and access to the first memory cell through the second port is controlled by a second word line; a second memory cell, wherein access to the second memory cell through the first port is controlled by the first word line, and access to the second memory cell through the second port is controlled by the second word line; and a disturb detector, used to generate a disturb detected signal for indicating whether the first memory cell and the second memory cell are accessed at a same time. A memory array having a write assistor is also disclosed.

公开(公告)号：US20230260558A1

公开(公告)日：2023-08-17

申请号：US17824738

申请日：2022-05-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ali Taghvaei ,  Atul Katoch

IPC分类号： G11C7/10 ,  G11C7/20 ,  G11C7/12

CPC分类号： G11C7/1048 ,  G11C7/20 ,  G11C7/12 ,  G11C7/1066 ,  G11C7/1093

摘要： Disclosed herein are related to a memory device. In one aspect, the memory device includes a memory cell, a precharge circuit, a reset voltage control circuit, and a logic control circuit. In one aspect, the precharge circuit is configured to set a voltage of the bit line to a first voltage level. In one aspect, the reset voltage control circuit includes a transistor coupled to the bit line to set the voltage of the bit line to a second voltage level. The transistor can be arranged or operate as a diode. In one aspect, the logic control circuit is configured to cause the reset voltage control circuit to set the voltage of the bit line to the second voltage level during a reset phase and cause the precharge circuit to set the voltage of the bit line to the first voltage level during a precharge phase after the reset phase.

公开(公告)号：US11295791B2

公开(公告)日：2022-04-05

申请号：US17027209

申请日：2020-09-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Atul Katoch ,  Ali Taghvaei

IPC分类号： G11C7/12 ,  G11C11/4091 ,  G11C16/04 ,  G11C7/10 ,  G11C7/06 ,  G11C7/18 ,  G11C11/419

摘要： A memory device Input/Output includes a memory cell having a local bit line. A first IO circuit is coupled to the local bit line and is configured to output a local IO signal to a global bit line. A second IO circuit is coupled to the global bit line and is configured to output a global IO signal. A latch circuit is configured to latch the local IO signal in response to a data signal on the local bit line.

公开(公告)号：US10783938B2

公开(公告)日：2020-09-22

申请号：US16273527

申请日：2019-02-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Atul Katoch ,  Ali Taghvaei

IPC分类号： G11C7/06 ,  G11C7/12 ,  G11C7/10 ,  G11C11/4091 ,  G11C7/18 ,  G11C16/04 ,  G11C11/419

摘要： A memory device Input/Output includes a memory cell having a local bit line. A first IO circuit is coupled to the local bit line and is configured to output a local IO signal to a global bit line. A second IO circuit is coupled to the global bit line and is configured to output a global IO signal. A latch circuit is configured to latch the local IO signal in response to a data signal on the local bit line.

公开(公告)号：US20210005232A1

公开(公告)日：2021-01-07

申请号：US17027209

申请日：2020-09-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Atul Katoch ,  Ali Taghvaei

IPC分类号： G11C7/12 ,  G11C7/10 ,  G11C11/4091 ,  G11C7/06 ,  G11C7/18 ,  G11C16/04 ,  G11C11/419

摘要： A memory device Input/Output includes a memory cell having a local bit line. A first IO circuit is coupled to the local bit line and is configured to output a local IO signal to a global bit line. A second IO circuit is coupled to the global bit line and is configured to output a global IO signal. A latch circuit is configured to latch the local IO signal in response to a data signal on the local bit line.