公开(公告)号：US11791834B2

公开(公告)日：2023-10-17

申请号：US17672378

申请日：2022-02-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Yu-Jie Huang ,  Mu-Shan Lin ,  Chien-Chun Tsai

IPC分类号： H03M1/66 ,  H03M1/74 ,  G05F3/16 ,  G05F3/26 ,  G05F3/20 ,  G05F1/59

CPC分类号： H03M1/747 ,  H03M1/662 ,  G05F1/59 ,  G05F3/16 ,  G05F3/205 ,  G05F3/262

摘要： A semiconductor circuit and a method of operating the same are provided. The semiconductor circuit comprises a first digital-to-analog converter configured to generate a first output current in response to a first binary code, and a second digital-to-analog converter configured to generate a second output current in response to a second binary code associated with the first binary code. The semiconductor circuit further comprises a first current-to-voltage converter configured to generate a first candidate voltage based on the first output current, and a second current-to-voltage converter configured to generate a second candidate voltage based on the second output current. The semiconductor circuit further comprises a multiplexer configured to output the target voltage based on the first candidate voltage or the second candidate voltage. The target voltage includes a configurable range associated with the second binary code.

公开(公告)号：US20220278091A1

公开(公告)日：2022-09-01

申请号：US17543255

申请日：2021-12-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chung-Hui Chen ,  Weichih Chen ,  Tien-Chien Huang ,  Chien-Chun Tsai ,  Ruey-Bin Sheen ,  Tsung-Hsin Yu ,  Chih-Hsien Chang ,  Cheng-Hsiang Hsieh

IPC分类号： H01L27/02 ,  H01L29/417 ,  H01L29/40 ,  H01L21/8234 ,  H01L27/088 ,  H03K17/687

摘要： A semiconductor structure including first finfet cells and second finfet cells. Each of the first finfet cells has an analog fin boundary according to analog circuit design rules, and each of the second finfet cells has a digital fin boundary according to digital circuit design rules. The semiconductor structure further includes first circuits formed with the first finfet cells, second circuits formed with the second finfet cells, and third circuits formed with one or more of the first finfet cells and one or more of the second finfet cells.

公开(公告)号：US09419615B2

公开(公告)日：2016-08-16

申请号：US14600727

申请日：2015-01-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Ying-Yu Hsu ,  Chien-Chun Tsai

IPC分类号： H03B1/00 ,  H03K3/00 ,  H03K19/0175

CPC分类号： H03K19/017509

摘要： A circuit comprises a voltage supply node, a reference voltage node, and a plurality of transistors coupled with the voltage supply node and the reference voltage node. The circuit also comprises a circuit input, a first delay element and a second delay element. The first delay element is coupled with the circuit input and one transistor of the plurality of transistors. The second delay element is coupled with the circuit input and a second transistor of the plurality of transistors. The circuit further comprises a circuit output coupled with the first transistor of the plurality of transistors and the second transistor of the plurality of transistors. The circuit additionally comprises a bias generator coupled with the circuit output, the first transistor of the plurality of transistors and the second transistor of the plurality of transistors.

摘要翻译： 电路包括电压供应节点，参考电压节点和与电压供应节点和参考电压节点耦合的多个晶体管。 电路还包括电路输入，第一延迟元件和第二延迟元件。 第一延迟元件与电路输入和多个晶体管中的一个晶体管耦合。 第二延迟元件与多个晶体管的电路输入端和第二晶体管耦合。 电路还包括与多个晶体管中的第一晶体管和多个晶体管的第二晶体管耦合的电路输出。 电路还包括与电路输出耦合的偏置发生器，多个晶体管中的第一晶体管和多个晶体管中的第二晶体管。