公开(公告)号：US09529268B2

公开(公告)日：2016-12-27

申请号：US14243985

申请日：2014-04-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Ming Chang ,  Chien-Fu Lee ,  Hoi-Tou Ng

IPC: G03F7/20

CPC classification number: G03F7/70058 ,  G03F7/70483

Abstract: Provided herein is a method of improving a transference of a mask pattern into a material layer on a semiconductor wafer. The method includes steps of receiving a semiconductor mask made from a desired design layout and of patterning the material layer present on a plurality of semiconductor wafers with the mask having the mask pattern and an illumination pattern. The method further includes steps of identifying defects and/or defect patterns in the transference of the mask pattern on the plurality of semiconductor wafers, determining an illumination modification, and applying the illumination modification to the illumination pattern to create a modified illumination pattern. Additional methods and associated systems are also provided.

Abstract translation: 本文提供了一种改善掩模图案转移到半导体晶片上的材料层中的方法。 该方法包括以下步骤：接收由期望的设计布局制成的半导体掩模，并且利用具有掩模图案的掩模和照明图案，使存在于多个半导体晶片上的材料层图案化。 该方法还包括以下步骤：识别在多个半导体晶片上的掩模图案的转移中的缺陷和/或缺陷图案，确定照明修改，以及将照明修改应用于照明图案以创建修改的照明图案。 还提供了附加的方法和相关系统。

公开(公告)号：US09672320B2

公开(公告)日：2017-06-06

申请号：US14754769

申请日：2015-06-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Ming Chang ,  Chien-Fu Lee ,  Chin-Yuan Tseng

IPC: G06F17/50 ,  G06F19/00 ,  G03F1/00 ,  G21K5/00

CPC classification number: G06F17/5081 ,  G03F1/00 ,  G03F1/68 ,  G03F1/70 ,  G06F19/00 ,  G06F2217/12 ,  G21K5/00

Abstract: A method of manufacturing an integrated circuit (IC) includes: receiving a target layout of the IC, decomposing the target layout into a plurality of sub-layouts for a multiple patterning process, identifying re-locatable pattern edges in the sub-layouts, and relocating the edges to improve manufacturability of the IC. In an embodiment, relocating the edges includes: choosing an evaluation index based on a target manufacturing process, moving one or more of the edges, calculating a score of manufacturability based on the evaluation index, and repeating the moving and the calculating until the score meets a threshold.

公开(公告)号：US20170004242A1

公开(公告)日：2017-01-05

申请号：US14754769

申请日：2015-06-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Ming Chang ,  Chien-Fu Lee ,  Chin-Yuan Tseng

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/00 ,  G03F1/68 ,  G03F1/70 ,  G06F19/00 ,  G06F2217/12 ,  G21K5/00

Abstract: A method of manufacturing an integrated circuit (IC) includes: receiving a target layout of the IC, decomposing the target layout into a plurality of sub-layouts for a multiple patterning process, identifying re-locatable pattern edges in the sub-layouts, and relocating the edges to improve manufacturability of the IC. In an embodiment, relocating the edges includes: choosing an evaluation index based on a target manufacturing process, moving one or more of the edges, calculating a score of manufacturability based on the evaluation index, and repeating the moving and the calculating until the score meets a threshold.

Abstract translation: 一种制造集成电路（IC）的方法包括：接收IC的目标布局，将目标布局分解为用于多个图案化处理的多个子布局，识别子布局中的可重新定位的图案边缘;以及 重新定位边缘以提高IC的可制造性。 在一个实施例中，重新定位边缘包括：基于目标制造过程选择评估指标，移动一个或多个边缘，基于评估指标计算可制造性的分数，并重复移动和计算，直到得分满足 一个门槛。

公开(公告)号：US20150286146A1

公开(公告)日：2015-10-08

申请号：US14243985

申请日：2014-04-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Ming Chang ,  Chien-Fu Lee ,  Hoi-Tou Ng

IPC: G03F7/20

CPC classification number: G03F7/70058 ,  G03F7/70483

Abstract: Provided herein is a method of improving a transference of a mask pattern into a material layer on a semiconductor wafer. The method includes steps of receiving a semiconductor mask made from a desired design layout and of patterning the material layer present on a plurality of semiconductor wafers with the mask having the mask pattern and an illumination pattern. The method further includes steps of identifying defects and/or defect patterns in the transference of the mask pattern on the plurality of semiconductor wafers, determining an illumination modification, and applying the illumination modification to the illumination pattern to create a modified illumination pattern. Additional methods and associated systems are also provided.

Abstract translation: 本文提供了一种改善掩模图案转移到半导体晶片上的材料层中的方法。 该方法包括以下步骤：接收由期望的设计布局制成的半导体掩模，并且利用具有掩模图案的掩模和照明图案，使存在于多个半导体晶片上的材料层图案化。 该方法还包括以下步骤：识别在多个半导体晶片上的掩模图案的转移中的缺陷和/或缺陷图案，确定照明修改，以及将照明修改应用于照明图案以创建修改的照明图案。 还提供了附加的方法和相关系统。