公开(公告)号：US10049885B2

公开(公告)日：2018-08-14

申请号：US15012205

申请日：2016-02-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hoi-Tou Ng ,  Kuei-Liang Lu ,  Ming-Feng Shieh ,  Ru-Gun Liu

IPC分类号： H01L21/308 ,  H01L21/033 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8234 ,  H01L21/027

摘要： A method for patterning fins for FinFET devices are disclosed. The method includes forming elongated protrusions on a semiconductor substrate and forming a mask covering a first portion of the elongated protrusions. The method further includes forming a spacer surrounding the mask. The mask and the spacer together cover a second portion of the elongated protrusions. The method further includes removing a portion of the elongated protrusions not covered by the mask and the spacer. In an embodiment, an outer boundary of the spacer and the mask corresponds to an outer boundary of a non-rectangular pattern.

公开(公告)号：US20160148815A1

公开(公告)日：2016-05-26

申请号：US15012205

申请日：2016-02-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hoi-Tou Ng ,  Kuei-Liang Lu ,  Ming-Feng Shieh ,  Ru-Gun Liu

IPC分类号： H01L21/308 ,  H01L21/8234 ,  H01L21/027

CPC分类号： H01L21/3086 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3088 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211

摘要： A method for patterning fins for FinFET devices are disclosed. The method includes forming elongated protrusions on a semiconductor substrate and forming a mask covering a first portion of the elongated protrusions. The method further includes forming a spacer surrounding the mask. The mask and the spacer together cover a second portion of the elongated protrusions. The method further includes removing a portion of the elongated protrusions not covered by the mask and the spacer. In an embodiment, an outer boundary of the spacer and the mask corresponds to an outer boundary of a non-rectangular pattern.

摘要翻译： 公开了用于FinFET器件的翅片图案的方法。 该方法包括在半导体衬底上形成细长突起并形成覆盖细长突起的第一部分的掩模。 所述方法还包括形成围绕所述掩模的间隔物。 掩模和间隔件一起覆盖细长突起的第二部分。 该方法还包括去除未被掩模和间隔物覆盖的细长突起的一部分。 在一个实施例中，间隔物和掩模的外边界对应于非矩形图案的外边界。

公开(公告)号：US20150286146A1

公开(公告)日：2015-10-08

申请号：US14243985

申请日：2014-04-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Ming Chang ,  Chien-Fu Lee ,  Hoi-Tou Ng

IPC分类号： G03F7/20

CPC分类号： G03F7/70058 ,  G03F7/70483

摘要： Provided herein is a method of improving a transference of a mask pattern into a material layer on a semiconductor wafer. The method includes steps of receiving a semiconductor mask made from a desired design layout and of patterning the material layer present on a plurality of semiconductor wafers with the mask having the mask pattern and an illumination pattern. The method further includes steps of identifying defects and/or defect patterns in the transference of the mask pattern on the plurality of semiconductor wafers, determining an illumination modification, and applying the illumination modification to the illumination pattern to create a modified illumination pattern. Additional methods and associated systems are also provided.

摘要翻译： 本文提供了一种改善掩模图案转移到半导体晶片上的材料层中的方法。 该方法包括以下步骤：接收由期望的设计布局制成的半导体掩模，并且利用具有掩模图案的掩模和照明图案，使存在于多个半导体晶片上的材料层图案化。 该方法还包括以下步骤：识别在多个半导体晶片上的掩模图案的转移中的缺陷和/或缺陷图案，确定照明修改，以及将照明修改应用于照明图案以创建修改的照明图案。 还提供了附加的方法和相关系统。

公开(公告)号：US20140365982A1

公开(公告)日：2014-12-11

申请号：US14465449

申请日：2014-08-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ru-Gun Liu ,  Shou-Yen Chou ,  Hoi-Tou Ng ,  Ken-Hsien Hsieh ,  Yi-Yin Chen

IPC分类号： G03F1/36 ,  G06F17/50

CPC分类号： G03F1/36 ,  G03F1/14 ,  G03F1/144 ,  G03F7/701 ,  G03F7/70433 ,  G03F7/70441 ,  G06F17/5068

摘要： A method for making a mask includes receiving an integrated circuit (IC) design layout and identifying at least one targeted-feature-surrounding-location (TFSL) in the IC design layout, wherein TFSL is identified by a model-based approach. The method further includes inserting at least one phase bar (PB) in the IC design layout and performing an optical proximity correction (OPC) to the IC design layout having the at least one PB to form a modified IC design layout. A mask is then fabricated based on the modified IC design layout.

摘要翻译： 制造掩模的方法包括接收集成电路（IC）设计布局并且识别IC设计布局中的至少一个目标特征周围位置（TFSL），其中TFSL通过基于模型的方法来识别。 该方法还包括在IC设计布局中插入至少一个相位条（PB），并且对具有至少一个PB的IC设计布局执行光学邻近校正（OPC）以形成修改的IC设计布局。 然后基于改进的IC设计布局制造掩模。

公开(公告)号：US09252021B2

公开(公告)日：2016-02-02

申请号：US14485168

申请日：2014-09-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hoi-Tou Ng ,  Kuei-Liang Lu ,  Ming-Feng Shieh ,  Ru-Gun Liu

IPC分类号： H01L21/308 ,  H01L21/84 ,  H01L27/12

CPC分类号： H01L21/3086 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3088 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211

摘要： Methods for patterning fins for fin-like field-effect transistor (FinFET) devices are disclosed. An exemplary method includes providing a semiconductor substrate, forming a plurality of elongated protrusions on the semiconductor substrate, the elongated protrusions extending in a first direction, and forming a mask covering a first portion of the elongated protrusions, the mask being formed of a first material having a first etch rate. The method also includes forming a spacer surrounding the mask, the spacer being formed of a second material with an etch rate lower than the etch rate of the first material, the mask and the spacer together covering a second portion of the elongated protrusions larger than the first portion of the elongated protrusions. Further, the method includes removing a remaining portion of the plurality of elongated protrusions not covered by the mask and spacer.

摘要翻译： 公开了用于翅片状场效应晶体管（FinFET）器件的图案形成方法。 一种示例性方法包括提供半导体衬底，在半导体衬底上形成多个细长突起，细长突起沿第一方向延伸，以及形成覆盖细长突起的第一部分的掩模，掩模由第一材料形成 具有第一蚀刻速率。 该方法还包括形成围绕掩模的间隔物，间隔物由蚀刻速率低于第一材料的蚀刻速率的第二材料形成，掩模和间隔物一起覆盖细长突起的第二部分， 细长突起的第一部分。 此外，该方法包括去除未被掩模和隔离物覆盖的多个细长突起的剩余部分。

公开(公告)号：US20150072527A1

公开(公告)日：2015-03-12

申请号：US14485168

申请日：2014-09-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hoi-Tou Ng ,  Kuei-Liang Lu ,  Ming-Feng Shieh ,  Ru-Gun Liu

IPC分类号： H01L21/308

CPC分类号： H01L21/3086 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3088 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211

摘要： Methods for patterning fins for fin-like field-effect transistor (FinFET) devices are disclosed. An exemplary method includes providing a semiconductor substrate, forming a plurality of elongated protrusions on the semiconductor substrate, the elongated protrusions extending in a first direction, and forming a mask covering a first portion of the elongated protrusions, the mask being formed of a first material having a first etch rate. The method also includes forming a spacer surrounding the mask, the spacer being formed of a second material with an etch rate lower than the etch rate of the first material, the mask and the spacer together covering a second portion of the elongated protrusions larger than the first portion of the elongated protrusions. Further, the method includes removing a remaining portion of the plurality of elongated protrusions not covered by the mask and spacer.

摘要翻译： 公开了用于翅片状场效应晶体管（FinFET）器件的图案形成方法。 一种示例性方法包括提供半导体衬底，在半导体衬底上形成多个细长突起，细长突起沿第一方向延伸，以及形成覆盖细长突起的第一部分的掩模，掩模由第一材料形成 具有第一蚀刻速率。 该方法还包括形成围绕掩模的间隔物，间隔物由蚀刻速率低于第一材料的蚀刻速率的第二材料形成，掩模和间隔物一起覆盖细长突起的第二部分， 细长突起的第一部分。 此外，该方法包括去除未被掩模和隔离物覆盖的多个细长突起的剩余部分。

公开(公告)号：US09529268B2

公开(公告)日：2016-12-27

申请号：US14243985

申请日：2014-04-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Ming Chang ,  Chien-Fu Lee ,  Hoi-Tou Ng

IPC分类号： G03F7/20

CPC分类号： G03F7/70058 ,  G03F7/70483

摘要： Provided herein is a method of improving a transference of a mask pattern into a material layer on a semiconductor wafer. The method includes steps of receiving a semiconductor mask made from a desired design layout and of patterning the material layer present on a plurality of semiconductor wafers with the mask having the mask pattern and an illumination pattern. The method further includes steps of identifying defects and/or defect patterns in the transference of the mask pattern on the plurality of semiconductor wafers, determining an illumination modification, and applying the illumination modification to the illumination pattern to create a modified illumination pattern. Additional methods and associated systems are also provided.

摘要翻译： 本文提供了一种改善掩模图案转移到半导体晶片上的材料层中的方法。 该方法包括以下步骤：接收由期望的设计布局制成的半导体掩模，并且利用具有掩模图案的掩模和照明图案，使存在于多个半导体晶片上的材料层图案化。 该方法还包括以下步骤：识别在多个半导体晶片上的掩模图案的转移中的缺陷和/或缺陷图案，确定照明修改，以及将照明修改应用于照明图案以创建修改的照明图案。 还提供了附加的方法和相关系统。

公开(公告)号：US09448470B2

公开(公告)日：2016-09-20

申请号：US14465449

申请日：2014-08-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ru-Gun Liu ,  Shou-Yen Chou ,  Hoi-Tou Ng ,  Ken-Hsien Hsieh ,  Yi-Yin Chen

IPC分类号： G06F17/50 ,  G03F1/36 ,  G03F7/20 ,  G03F1/00

CPC分类号： G03F1/36 ,  G03F1/14 ,  G03F1/144 ,  G03F7/701 ,  G03F7/70433 ,  G03F7/70441 ,  G06F17/5068

摘要： A method for making a mask includes receiving an integrated circuit (IC) design layout and identifying at least one targeted-feature-surrounding-location (TFSL) in the IC design layout, wherein TFSL is identified by a model-based approach. The method further includes inserting at least one phase bar (PB) in the IC design layout and performing an optical proximity correction (OPC) to the IC design layout having the at least one PB to form a modified IC design layout. A mask is then fabricated based on the modified IC design layout.

摘要翻译： 制造掩模的方法包括接收集成电路（IC）设计布局并且识别IC设计布局中的至少一个目标特征周围位置（TFSL），其中TFSL通过基于模型的方法来识别。 该方法还包括在IC设计布局中插入至少一个相位条（PB），并且对具有至少一个PB的IC设计布局执行光学邻近校正（OPC）以形成修改的IC设计布局。 然后基于改进的IC设计布局制造掩模。