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    3D structure for advanced SRAM design to avoid half-selected issue
    1.
    发明授权
    3D structure for advanced SRAM design to avoid half-selected issue 有权

    公开(公告)号：US10163489B2

    公开(公告)日：2018-12-25

    申请号：US15865923

    申请日：2018-01-09

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chien-Yuan Chen ,  Chien-Yu Huang ,  Hau-Tai Shieh

    IPC分类号： G11C11/418 ,  G11C5/02 ,  G11C8/08 ,  H01L25/065 ,  G11C11/412 ,  H01L27/11

    摘要： Systems are provided for a three dimension static random access memory (SRAM) structure. The SRAM structure comprises a plurality of memory array layers, layer decoder circuitry on each memory array layer, a word line driver circuit disposed on each memory array layer, and a plurality of complementary bit line pairs extending vertically from a memory cell in a first memory array layer to a memory cell in a second memory array layer. The layer decoder circuitry on each memory array layer is configured to decode a portion of an SRAM address to determine if the SRAM address corresponds to memory cells on its memory array layer. The word line driver circuit disposed on each memory array layer is configured to operate cooperatively with a partial SRAM address decoder to select and drive one of the plurality of word lines disposed on its memory array layer, wherein a selected word line is connected to a predetermined number of memory cells in a specific memory array layer.

    3D structure for advanced SRAM design to avoid half-selected issue
    5.
    发明授权
    3D structure for advanced SRAM design to avoid half-selected issue 有权

    公开(公告)号：US10354719B2

    公开(公告)日：2019-07-16

    申请号：US16226956

    申请日：2018-12-20

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chien-Yuan Chen ,  Chien-Yu Huang ,  Hau-Tai Shieh

    IPC分类号： G11C11/418 ,  G11C5/02 ,  G11C8/08 ,  H01L25/065 ,  G11C11/412 ,  H01L27/11

    摘要： Systems are provided for a three dimension static random access memory (SRAM) structure. The SRAM structure comprises a plurality of memory array layers, layer decoder circuitry on each memory array layer, a word line driver circuit disposed on each memory array layer, and a plurality of complementary bit line pairs extending vertically from a memory cell in a first memory array layer to a memory cell in a second memory array layer. The layer decoder circuitry on each memory array layer is configured to decode a portion of an SRAM address to determine if the SRAM address corresponds to memory cells on its memory array layer. The word line driver circuit disposed on each memory array layer is configured to operate cooperatively with a partial SRAM address decoder to select and drive one of the plurality of word lines disposed on its memory array layer, wherein a selected word line is connected to a predetermined number of memory cells in a specific memory array layer.