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公开(公告)号：US20220352223A1
公开(公告)日：2022-11-03
申请号：US17865623
申请日：2022-07-15
发明人： Chun-Yuan Chen , Ching-Chun Wang , Hsiao-Hui Tseng , Jen-Cheng Liu , Jhy-Jyi Sze , Shyh-Fann Ting , Wei Chuang Wu , Yen-Ting Chiang , Chia Ching Liao , Yen-Yu Chen
IPC分类号： H01L27/146 , H01L29/423
摘要： In some embodiments, the present disclosure relates to a device having a semiconductor substrate including a frontside and a backside. On the frontside of the semiconductor substrate are a first source/drain region and a second source/drain region. A gate electrode is arranged on the frontside of the semiconductor substrate and includes a horizontal portion, a first vertical portion, and a second vertical portion. The horizontal portion is arranged over the frontside of the semiconductor substrate and between the first and second source/drain regions. The first vertical portion extends from the frontside towards the backside of the semiconductor substrate and contacts the horizontal portion of the gate electrode structure. The second vertical portion extends from the frontside towards the backside of the semiconductor substrate, contacts the horizontal portion of the gate electrode structure, and is separated from the first vertical portion by a channel region of the substrate.
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公开(公告)号：US11217621B2
公开(公告)日：2022-01-04
申请号：US15688351
申请日：2017-08-28
发明人： Cheng-Hsien Chou , Chih-Yu Lai , Shih Pei Chou , Yen-Ting Chiang , Hsiao-Hui Tseng , Min-Ying Tsai
IPC分类号： H01L27/146 , H01L29/06 , H01L21/762
摘要： A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.
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公开(公告)号：US10910420B2
公开(公告)日：2021-02-02
申请号：US16983767
申请日：2020-08-03
发明人： Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Tzu-Hsuan Hsu , Szu-Ying Chen , Wei-Cheng Hsu , Hsiao-Hui Tseng
IPC分类号： H01L27/146 , H01L31/18
摘要： A device including a gate structure formed over a semiconductor substrate, the gate structure having extensions, a device isolation structure formed into the semiconductor substrate adjacent the gate structure, wherein the extensions are over a portion of the device isolation structure, and source/drain regions on both sides of the gate structure, the source/drain regions being formed in a gap in the device isolation structure and being partially enclosed by the extensions of the gate structure.
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公开(公告)号：US20170309672A1
公开(公告)日：2017-10-26
申请号：US15645039
申请日：2017-07-10
发明人： Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Tzu-Hsuan Hsu , Szu-Ying Chen , Wei-Cheng Hsu , Hsiao-Hui Tseng
IPC分类号： H01L27/146 , H01L31/18
CPC分类号： H01L27/14614 , H01L27/1463 , H01L27/14643 , H01L27/14685 , H01L31/18
摘要： A device including a gate structure formed over a semiconductor substrate, the gate structure having extensions, a device isolation structure formed into the semiconductor substrate adjacent the gate structure, wherein the extensions are over a portion of the device isolation structure, and source/drain regions on both sides of the gate structure, the source/drain regions being formed in a gap in the device isolation structure and being partially enclosed by the extensions of the gate structure.
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公开(公告)号：US09704910B2
公开(公告)日：2017-07-11
申请号：US15075880
申请日：2016-03-21
发明人： Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Tzu-Hsuan Hsu , Szu-Ying Chen , Wei-Cheng Hsu , Hsiao-Hui Tseng
IPC分类号： H01L31/062 , H01L27/146 , H01L31/18
CPC分类号： H01L27/14614 , H01L27/1463 , H01L27/14643 , H01L27/14685 , H01L31/18
摘要： A device including a gate structure formed over a semiconductor substrate, the gate structure having extensions, a device isolation structure formed into the semiconductor substrate adjacent the gate structure, wherein the extensions are over a portion of the device isolation structure, and source/drain regions on both sides of the gate structure, the source/drain regions being formed in a gap in the device isolation structure and being partially enclosed by the extensions of the gate structure.
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公开(公告)号：US09293502B2
公开(公告)日：2016-03-22
申请号：US13951626
申请日：2013-07-26
发明人： Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Tzu-Hsuan Hsu , Szu-Ying Chen , Wei-Cheng Hsu , Hsiao-Hui Tseng
IPC分类号： H01L21/00 , H01L27/146 , H01L31/18
CPC分类号： H01L27/14614 , H01L27/1463 , H01L27/14643 , H01L27/14685 , H01L31/18
摘要： A device including a gate structure formed over a semiconductor substrate, the gate structure having extensions, a device isolation structure formed into the semiconductor substrate adjacent the gate structure, wherein the extensions are over a portion of the device isolation structure, and source/drain regions on both sides of the gate structure, the source/drain regions being formed in a gap in the device isolation structure and being partially enclosed by the extensions of the gate structure.
摘要翻译： 一种包括形成在半导体衬底上的栅极结构的器件，所述栅极结构具有延伸部分，与所述栅极结构相邻形成在所述半导体衬底中的器件隔离结构，其中所述延伸部分在所述器件隔离结构的一部分之上，以及源极/漏极区域 在栅极结构的两侧，源极/漏极区域形成在器件隔离结构中的间隙中，并被栅极结构的延伸部分封闭。
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公开(公告)号：US20150263214A1
公开(公告)日：2015-09-17
申请号：US14725480
申请日：2015-05-29
发明人： Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Chun-Chieh Chuang , Hsiao-Hui Tseng , Tzu-Hsuan Hsu
IPC分类号： H01L31/18 , H01L31/103 , H01L31/02 , H01L27/146
CPC分类号： H01L31/18 , H01L27/1461 , H01L27/14621 , H01L27/14627 , H01L27/1464 , H01L27/14689 , H01L31/02 , H01L31/103 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A method includes forming a first implantation mask comprising a first opening, implanting a first portion of a semiconductor substrate through the first opening to form a first doped region, forming a second implantation mask comprising a second opening, and implanting a second portion of the semiconductor substrate to form a second doped region. The first portion of the semiconductor substrate is encircled by the second portion of the semiconductor substrate. A surface layer of the semiconductor substrate is implanted to form a third doped region of an opposite conductivity type than the first and the second doped regions. The third doped region forms a diode with the first and the second doped regions.
摘要翻译： 一种方法包括形成包括第一开口的第一注入掩模，通过第一开口注入半导体衬底的第一部分以形成第一掺杂区，形成包括第二开口的第二注入掩模，以及注入半导体的第二部分 衬底以形成第二掺杂区域。 半导体衬底的第一部分被半导体衬底的第二部分包围。 注入半导体衬底的表面层以形成与第一和第二掺杂区相反导电类型的第三掺杂区。 第三掺杂区域形成具有第一和第二掺杂区域的二极管。
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公开(公告)号：US20200066774A1
公开(公告)日：2020-02-27
申请号：US16672723
申请日：2019-11-04
发明人： Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Tzu-Hsuan Hsu , Szu-Ying Chen , Wei-Cheng Hsu , Hsiao-Hui Tseng
IPC分类号： H01L27/146 , H01L31/18
摘要： A device including a gate structure formed over a semiconductor substrate, the gate structure having extensions, a device isolation structure formed into the semiconductor substrate adjacent the gate structure, wherein the extensions are over a portion of the device isolation structure, and source/drain regions on both sides of the gate structure, the source/drain regions being formed in a gap in the device isolation structure and being partially enclosed by the extensions of the gate structure.
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公开(公告)号：US20170373117A1
公开(公告)日：2017-12-28
申请号：US15688351
申请日：2017-08-28
发明人： Cheng-Hsien Chou , Chih-Yu Lai , Shih Pei Chou , Yen-Ting Chiang , Hsiao-Hui Tseng , Min-Ying Tsai
IPC分类号： H01L27/146 , H01L21/762 , H01L29/06
CPC分类号： H01L27/14687 , H01L21/76229 , H01L27/1463 , H01L29/0653
摘要： A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.
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公开(公告)号：US09754993B2
公开(公告)日：2017-09-05
申请号：US14840944
申请日：2015-08-31
发明人： Cheng-Hsien Chou , Hsiao-Hui Tseng , Chih-Yu Lai , Shih Pei Chou , Yen-Ting Chiang , Min-Ying Tsai
IPC分类号： H01L21/762 , H01L27/146 , H01L29/06
CPC分类号： H01L27/14687 , H01L21/76205 , H01L21/76224 , H01L21/76229 , H01L21/76232 , H01L27/1463 , H01L29/0653
摘要： A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.
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