-
公开(公告)号：US12068747B2
公开(公告)日：2024-08-20
申请号：US17718456
申请日：2022-04-12
Inventor： Szu-Lin Liu , Bei-Shing Lien , Yi-Wen Chen , Chin-Ho Chang , Jaw-Juinn Horng , Yung-Chow Peng
CPC classification number: H03K3/011 , H03F3/45475
Abstract: A semiconductor device includes a temperature-independent current generator that generates a reference current substantially independent of temperature and a mirror current that is a substantial duplicate of the reference current, a pulse signal generator that samples the mirror current so as to generate a pulse signal, and a counter that obtains a number of pulse signals generated by the pulse signal generator, that permits the pulse signal generator to generate a pulse signal when it is determined thereby that the number of pulse signals obtained thereby is less than a predetermined threshold value, and that inhibits the pulse signal generator from generating a pulse signal when it is determined thereby that the number of pulse signals obtained thereby is equal to the predetermined threshold value. A method for monitoring a temperature of the semiconductor device is also disclosed.
-
公开(公告)号：US11756950B2
公开(公告)日：2023-09-12
申请号：US17363355
申请日：2021-06-30
Inventor： Chin-Ho Chang , Yi-Wen Chen , Jaw-Juinn Horng , Yung-Chow Peng
IPC: H01L27/02 , H01L21/8238 , H01L27/092
CPC classification number: H01L27/0207 , H01L21/823871 , H01L27/092
Abstract: An integrated circuit includes a first circuit with m first units coupled in parallel, any of the first units including one or more first transistors coupled in series, and a second circuit with n second units coupled in parallel, any of the second units including one or more second transistors coupled in series. A gate terminal of the first circuit is coupled to a gate terminal of the second circuit. M and n are different positive integers.
-
公开(公告)号：US20230178605A1
公开(公告)日：2023-06-08
申请号：US17545825
申请日：2021-12-08
Inventor： Jaw-Juinn Horng , Yi-Wen Chen , Chin-Ho Chang , Po-Yu Lai , Yung-Chow Peng
IPC: H01L29/06 , H01L27/088 , H01L29/40
CPC classification number: H01L29/0696 , H01L27/088 , H01L29/401
Abstract: A device including at least one transistor cell including metal-oxide semiconductor field-effect transistors each having drain/source terminals and a channel length. The at least one transistor cell includes a first number of transistors of the metal-oxide semiconductor field-effect transistors connected in series, with one of the drain/source terminals of one of the first number of transistors connected to one of the drain/source terminals of another one of the first number of transistors and gates of the first number of transistors connected together. The at least one transistor cell configured to be used to provide a transistor having a longer channel length than the channel length of each of the metal-oxide semiconductor field-effect transistors.
-
公开(公告)号：US20230063492A1
公开(公告)日：2023-03-02
申请号：US17458707
申请日：2021-08-27
Inventor： Szu-Chun Tsao , Jaw-Juinn Horng , Bindu Madhavi Kasina , Yi-Wen Chen
Abstract: Systems and methods as described herein may take a variety of forms. In one example, systems and methods are provided for a circuit for powering a voltage regulator. A voltage regulator circuit has an output electrically coupled to a gate of an output driver transistor, the output driver transistor having a first terminal electrically coupled to a voltage source and a second terminal electrically coupled to a first terminal of a voltage divider, the voltage divider having an second terminal electrically coupled to ground, and the voltage divider having an output of a stepped down voltage. A power control circuitry transistor has a first terminal electrically coupled to the voltage source, the power control circuitry transistor having a second terminal electrically coupled to the gate terminal of the output driver transistor, and the power control circuitry transistor having a gate terminal electrically coupled to a status voltage signal.
-
公开(公告)号：US20220223579A1
公开(公告)日：2022-07-14
申请号：US17363355
申请日：2021-06-30
Inventor： Chin-Ho Chang , Yi-Wen Chen , Jaw-Juinn Horng , Yung-Chow Peng
IPC: H01L27/02 , H01L27/092 , H01L21/8238
Abstract: An integrated circuit includes a first circuit with m first units coupled in parallel, any of the first units including one or more first transistors coupled in series, and a second circuit with n second units coupled in parallel, any of the second units including one or more second transistors coupled in series. A gate terminal of the first circuit is coupled to a gate terminal of the second circuit. M and n are different positive integers.
-
Patent Agency Ranking
公开(公告)号：US20240364315A1
公开(公告)日：2024-10-31
申请号：US18770826
申请日：2024-07-12
Inventor： Szu-Lin Liu , Bei-Shing Lien , Yi-Wen Chen , Chin-Ho Chang , Jaw-Juinn Horng , Yung-Chow Peng
CPC classification number: H03K3/011 , H03F3/45475
Abstract: A semiconductor device includes a temperature-independent current generator that generates a reference current substantially independent of temperature and a mirror current that is a substantial duplicate of the reference current, a pulse signal generator that samples the mirror current so as to generate a pulse signal, and a counter that obtains a number of pulse signals generated by the pulse signal generator, that permits the pulse signal generator to generate a pulse signal when it is determined thereby that the number of pulse signals obtained thereby is less than a predetermined threshold value, and that inhibits the pulse signal generator from generating a pulse signal when it is determined thereby that the number of pulse signals obtained thereby is equal to the predetermined threshold value. A method for monitoring a temperature of the semiconductor device is also disclosed.
-
公开(公告)号：US20230244258A1
公开(公告)日：2023-08-03
申请号：US18296474
申请日：2023-04-06
Inventor： Szu-Chun Tsao , Jaw-Juinn Horng , Bindu Madhavi Kasina , Yi-Wen Chen
Abstract: Systems and methods as described herein may take a variety of forms. In one example, systems and methods are provided for a circuit for powering a voltage regulator. A voltage regulator circuit has an output electrically coupled to a gate of an output driver transistor, the output driver transistor having a first terminal electrically coupled to a voltage source and a second terminal electrically coupled to a first terminal of a voltage divider, the voltage divider having an second terminal electrically coupled to ground, and the voltage divider having an output of a stepped down voltage. A power control circuitry transistor has a first terminal electrically coupled to the voltage source, the power control circuitry transistor having a second terminal electrically coupled to the gate terminal of the output driver transistor, and the power control circuitry transistor having a gate terminal electrically coupled to a status voltage signal.
-
公开(公告)号：US20230049398A1
公开(公告)日：2023-02-16
申请号：US17718456
申请日：2022-04-12
Inventor： Szu-Lin Liu , Bei-Shing Lien , Yi-Wen Chen , Chin-Ho Chang , Jaw-Juinn Horng , Yung-Chow Peng
Abstract: A semiconductor device includes a temperature-independent current generator that generates a reference current substantially independent of temperature and a mirror current that is a substantial duplicate of the reference current, a pulse signal generator that samples the mirror current so as to generate a pulse signal, and a counter that obtains a number of pulse signals generated by the pulse signal generator, that permits the pulse signal generator to generate a pulse signal when it is determined thereby that the number of pulse signals obtained thereby is less than a predetermined threshold value, and that inhibits the pulse signal generator from generating a pulse signal when it is determined thereby that the number of pulse signals obtained thereby is equal to the predetermined threshold value. A method for monitoring a temperature of the semiconductor device is also disclosed.
-
公开(公告)号：US20220365550A1
公开(公告)日：2022-11-17
申请号：US17456934
申请日：2021-11-30
Inventor： Szu-Chun Tsao , Yi-Wen Chen , Jaw-Juinn Horng
IPC: G05F1/575 , H03K19/0185 , G05F1/565
Abstract: A middle-range (mid) low dropout (LDO) voltage has both sinking and sourcing current capability. The mid LDO can provide a voltage reference in active mode and power mode for core only design to work in a Safe Operating Area (SOA). The output of mid LDO can track TO power and/or core power dynamically. The mid LDO can comprise a voltage reference generator and a power-down controller connected to an amplifier, which output is connected to a decoupling capacitor. The provision of a high ground signal allows the mid LDO provide the sinking and sourcing currents.
-
公开(公告)号：US11086348B2
公开(公告)日：2021-08-10
申请号：US16682683
申请日：2019-11-13
Inventor： Jaw-Juinn Horng , Chin-Ho Chang , Yi-Wen Chen
Abstract: A bandgap reference (BGR) circuit is provided. The BGR circuit includes a first node, a second node, and a third node. A first resistive element is connected between the second node and the third node. The BGR circuit is operative to provide a reference voltage as an output. The BGR circuit further includes a current shunt path connected between the first node and the third node, the current shunt path being operable to regulate a voltage drop across the first resistive element.
-
-
-
-
-
-
-
-
-
Search Results
19
records
(took 0.023 seconds)
