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公开(公告)号：US12132081B2
公开(公告)日：2024-10-29
申请号：US17545825
申请日：2021-12-08
发明人： Jaw-Juinn Horng , Yi-Wen Chen , Chin-Ho Chang , Po-Yu Lai , Yung-Chow Peng
IPC分类号： H01L29/06 , H01L27/088 , H01L29/40
CPC分类号： H01L29/0696 , H01L27/088 , H01L29/401
摘要： A device including at least one transistor cell including metal-oxide semiconductor field-effect transistors each having drain/source terminals and a channel length. The at least one transistor cell includes a first number of transistors of the metal-oxide semiconductor field-effect transistors connected in series, with one of the drain/source terminals of one of the first number of transistors connected to one of the drain/source terminals of another one of the first number of transistors and gates of the first number of transistors connected together. The at least one transistor cell configured to be used to provide a transistor having a longer channel length than the channel length of each of the metal-oxide semiconductor field-effect transistors.
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公开(公告)号：US12088264B2
公开(公告)日：2024-09-10
申请号：US18446031
申请日：2023-08-08
发明人： Chin-Ho Chang , Jaw-Juinn Horng , Yung-Chow Peng
CPC分类号： H03F3/45076 , G11C7/12 , H03M1/38 , H03F2203/45156
摘要： A method of amplifying an input voltage based on cascaded charge pump includes generating, at a set of capacitors, an input voltage corresponding to input data. The method further includes storing, by a first capacitor, first electrical charges corresponding to the input voltage to obtain a second voltage. The method further includes amplifying, a voltage amplifier, the second voltage according to the first electrical charges stored by the first capacitor to obtain a third voltage. The method further includes storing, by a second capacitor, second electrical charges according to the third voltage. The method further includes amplifying, by the voltage amplifier, the third voltage according to the second electrical charges stored by the second capacitor to obtain a fourth voltage.
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公开(公告)号：US11430491B2
公开(公告)日：2022-08-30
申请号：US17185145
申请日：2021-02-25
发明人： Jaw-Juinn Horng , Chin-Ho Chang , Yung-Chow Peng , Szu-Chun Tsao
摘要： In a compute-in-memory (“CIM”) system, current signals, indicative of the result of a multiply-and-accumulate operation, from a CIM memory circuit are computed by comparing them with reference currents, which are generated by a current digital-to-analog converter (“DAC”) circuit. The memory circuit can include non-volatile memory (“NVM”) elements, which can be multi-level or two-level NVM elements. The characteristic sizes of the memory elements can be binary weighted to correspond to the respective place values in a multi-bit weight and/or a multi-bit input signal. Alternatively, NVM elements of equal size can be used to drive transistors of binary weighted sizes. The current comparison operation can be carried out at higher speeds than voltage computation. In some embodiments, simple clock-gated switches are used to produce even currents in the current summing branches. The clock-gated switches also serve to limit the time the cell currents are on, thereby reducing static power consumption.
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公开(公告)号：US20200381027A1
公开(公告)日：2020-12-03
申请号：US16881380
申请日：2020-05-22
发明人： Jaw-Juinn Horng , Chin-Ho Chang , Yung-Chow Peng
摘要： A computing device in some examples includes multiple digital-to-analog converters (DACs) having outputs connected to respective operational amplifiers, with outputs connected to the gates of respective transistors, each forming a serial combination with a respective memory element. The serial combinations are connected between a voltage reference point and a conductive line. An analog-to-digital converter is connected to the conductive line at the input. The DACs generate analog signals having ON-periods of lengths corresponding to the respective numbers at the DACs' inputs. The transistors generate currents indicative of the level of output signals of the respective DACs and memory states of the respective memory elements for the ON-periods. The combined currents charges or discharges the conductive line, which has a parasitic capacitance, to a voltage, which is indicative of the sum of the numbers weighted by the memory states. The voltage is converted to a digital representation of the weighted sum.
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公开(公告)号：US11614764B2
公开(公告)日：2023-03-28
申请号：US17396981
申请日：2021-08-09
发明人： Jaw-Juinn Horng , Chin-Ho Chang , Yi-Wen Chen
摘要： A bandgap reference (BGR) circuit is provided. The BGR circuit includes a first node, a second node, and a third node. A first resistive element is connected between the second node and the third node. The BGR circuit is operative to provide a reference voltage as an output. The BGR circuit further includes a current shunt path connected between the first node and the third node, the current shunt path being operable to regulate a voltage drop across the first resistive element.
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公开(公告)号：US20240364315A1
公开(公告)日：2024-10-31
申请号：US18770826
申请日：2024-07-12
发明人： Szu-Lin Liu , Bei-Shing Lien , Yi-Wen Chen , Chin-Ho Chang , Jaw-Juinn Horng , Yung-Chow Peng
CPC分类号： H03K3/011 , H03F3/45475
摘要： A semiconductor device includes a temperature-independent current generator that generates a reference current substantially independent of temperature and a mirror current that is a substantial duplicate of the reference current, a pulse signal generator that samples the mirror current so as to generate a pulse signal, and a counter that obtains a number of pulse signals generated by the pulse signal generator, that permits the pulse signal generator to generate a pulse signal when it is determined thereby that the number of pulse signals obtained thereby is less than a predetermined threshold value, and that inhibits the pulse signal generator from generating a pulse signal when it is determined thereby that the number of pulse signals obtained thereby is equal to the predetermined threshold value. A method for monitoring a temperature of the semiconductor device is also disclosed.
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公开(公告)号：US20230049398A1
公开(公告)日：2023-02-16
申请号：US17718456
申请日：2022-04-12
发明人： Szu-Lin Liu , Bei-Shing Lien , Yi-Wen Chen , Chin-Ho Chang , Jaw-Juinn Horng , Yung-Chow Peng
摘要： A semiconductor device includes a temperature-independent current generator that generates a reference current substantially independent of temperature and a mirror current that is a substantial duplicate of the reference current, a pulse signal generator that samples the mirror current so as to generate a pulse signal, and a counter that obtains a number of pulse signals generated by the pulse signal generator, that permits the pulse signal generator to generate a pulse signal when it is determined thereby that the number of pulse signals obtained thereby is less than a predetermined threshold value, and that inhibits the pulse signal generator from generating a pulse signal when it is determined thereby that the number of pulse signals obtained thereby is equal to the predetermined threshold value. A method for monitoring a temperature of the semiconductor device is also disclosed.
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公开(公告)号：US11086348B2
公开(公告)日：2021-08-10
申请号：US16682683
申请日：2019-11-13
发明人： Jaw-Juinn Horng , Chin-Ho Chang , Yi-Wen Chen
摘要： A bandgap reference (BGR) circuit is provided. The BGR circuit includes a first node, a second node, and a third node. A first resistive element is connected between the second node and the third node. The BGR circuit is operative to provide a reference voltage as an output. The BGR circuit further includes a current shunt path connected between the first node and the third node, the current shunt path being operable to regulate a voltage drop across the first resistive element.
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公开(公告)号：US10520972B2
公开(公告)日：2019-12-31
申请号：US16195176
申请日：2018-11-19
发明人： Jaw-Juinn Horng , Chin-Ho Chang , Yi-Wen Chen
摘要： A bandgap reference (BGR) circuit is provided. The BGR circuit includes a first node, a second node, and a third node. A first resistive element is connected between the second node and the third node. The BGR circuit is operative to provide a reference voltage as an output. The BGR circuit further includes a current shunt path connected between the first node and the third node, the current shunt path being operable to regulate a voltage drop across the first resistive element.
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公开(公告)号：US20210343320A1
公开(公告)日：2021-11-04
申请号：US17185145
申请日：2021-02-25
发明人： Jaw-Juinn Horng , Chin-Ho Chang , Yung-Chow Peng , Szu-Chun Tsao
摘要： In a compute-in-memory (“CIM”) system, current signals, indicative of the result of a multiply-and-accumulate operation, from a CIM memory circuit are computed by comparing them with reference currents, which are generated by a current digital-to-analog converter (“DAC”) circuit. The memory circuit can include non-volatile memory (“NVM”) elements, which can be multi-level or two-level NVM elements. The characteristic sizes of the memory elements can be binary weighted to correspond to the respective place values in a multi-bit weight and/or a multi-bit input signal. Alternatively, NVM elements of equal size can be used to drive transistors of binary weighted sizes. The current comparison operation can be carried out at higher speeds than voltage computation. In some embodiments, simple clock-gated switches are used to produce even currents in the current summing branches. The clock-gated switches also serve to limit the time the cell currents are on, thereby reducing static power consumption.
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