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公开(公告)号：US09142614B2
公开(公告)日：2015-09-22
申请号：US13935810
申请日：2013-07-05
发明人： Ming Chyi Liu , Sheng-de Liu , Chi-Ming Chen , Che-Ming Chang , Chung-Yen Chou , Chia-Shiung Tsa
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/76232 , H01L21/30604 , H01L21/3065 , H01L21/308 , H01L21/76224 , H01L29/0649
摘要： Among other things, one or more semiconductor arrangements comprising isolation trenches, and techniques for forming such isolation trenches are provided. A substrate comprises a front side surface and a backside surface. One or more devices are formed over the front side surface. A wet etch is performed to form a tapered portion of an isolation trench. A dry etch is performed to form a non-tapered portion of the isolation trench. Because both the wet etch and the dry etch are performed, etching time is reduced compared to merely using the dry etch due to the wet etch having a relatively faster etch rate than the dry etch. In an embodiment, the isolation trench provides isolation for a current leakage path associated with a device or other material formed over the front side surface. In an embodiment, metal is formed within the isolation trench for backside metallization.
摘要翻译： 其中包括一个或多个包括隔离沟道的半导体布置，以及用于形成这种隔离沟槽的技术。 基板包括前侧表面和后侧表面。 一个或多个装置形成在前侧表面上。 执行湿蚀刻以形成隔离沟槽的锥形部分。 执行干蚀刻以形成隔离沟槽的非锥形部分。 因为执行了湿蚀刻和干蚀刻，所以与仅使用干蚀刻相比，由于湿刻蚀具有比干蚀刻更快的蚀刻速率，所以蚀刻时间减少。 在一个实施例中，隔离沟槽为与在前侧表面上形成的装置或其它材料相关联的电流泄漏路径提供隔离。 在一个实施例中，在用于背面金属化的隔离沟槽内形成金属。
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公开(公告)号：US11167982B2
公开(公告)日：2021-11-09
申请号：US16901339
申请日：2020-06-15
IPC分类号： H01L21/768 , B81C1/00
摘要： A semiconductor arrangement and methods of formation are provided. The semiconductor arrangement includes a micro-electro mechanical system (MEMS). A via opening is formed through a substrate, first dielectric layer and a first plug of the MEMS. The first plug comprises a first material, where the first material has an etch selectivity different than an etch selectivity of the first dielectric layer. The different etch selectivity of first plug allows the via opening to be formed relatively quickly and with a relatively high aspect ratio and desired a profile, as compared to forming the via opening without using the first plug.
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公开(公告)号：US10683204B2
公开(公告)日：2020-06-16
申请号：US16443174
申请日：2019-06-17
IPC分类号： H01L21/768 , B81C1/00
摘要： A semiconductor arrangement and methods of formation are provided. The semiconductor arrangement includes a micro-electro mechanical system (MEMS). A via opening is formed through a substrate, first dielectric layer and a first plug of the MEMS. The first plug comprises a first material, where the first material has an etch selectivity different than an etch selectivity of the first dielectric layer. The different etch selectivity of first plug allows the via opening to be formed relatively quickly and with a relatively high aspect ratio and desired a profile, as compared to forming the via opening without using the first plug.
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公开(公告)号：US09960285B2
公开(公告)日：2018-05-01
申请号：US13659219
申请日：2012-10-24
发明人： Chung-Yen Chou , Po-ken Lin , Shih-Chang Liu , Chia-Shiung Tsai
CPC分类号： H01L29/945
摘要： One or more techniques or systems for forming a contact structure for a deep trench capacitor (DTC) are provided herein. In some embodiments, a contact structure includes a substrate region, a first region, a second region, contact landings, a first trench region, a first landing region, and a second trench region. In some embodiments, a first region is over the substrate region and a second region is over the first region. For example, the first region and the second region are in the first trench region or the second trench region. Additionally, a contact landing over the first trench region, the second trench region, or the first landing region is in contact with the first region, the second region, or the substrate region. In this manner, additional contacts are provided and landing area is reduced, thus reducing resistance of the DTC, for example.
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公开(公告)号：US20160005642A1
公开(公告)日：2016-01-07
申请号：US14851544
申请日：2015-09-11
发明人： Ming Chyi Liu , Sheng-de Liu , Chi-Ming Chen , Che-Ming Chang , Chung-Yen Chou , Chia-Shiung Tsai
IPC分类号： H01L21/762 , H01L21/3065 , H01L21/308 , H01L21/306
CPC分类号： H01L21/76232 , H01L21/30604 , H01L21/3065 , H01L21/308 , H01L21/76224 , H01L29/0649
摘要： Among other things, one or more semiconductor arrangements comprising isolation trenches, and techniques for forming such isolation trenches are provided. A substrate comprises a front side surface and a backside surface. One or more devices are formed over the front side surface. A wet etch is performed to form a tapered portion of an isolation trench. A dry etch is performed to form a non-tapered portion of the isolation trench. Because both the wet etch and the dry etch are performed, etching time is reduced compared to merely using the dry etch due to the wet etch having a relatively faster etch rate than the dry etch. In an embodiment, the isolation trench provides isolation for a current leakage path associated with a device or other material formed over the front side surface. In an embodiment, metal is formed within the isolation trench for backside metallization.
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公开(公告)号：US09530685B2
公开(公告)日：2016-12-27
申请号：US14851544
申请日：2015-09-11
发明人： Ming Chyi Liu , Sheng-de Liu , Chi-Ming Chen , Che-Ming Chang , Chung-Yen Chou , Chia-Shiung Tsai
IPC分类号： H01L21/762 , H01L29/06 , H01L21/306 , H01L21/3065 , H01L21/308
CPC分类号： H01L21/76232 , H01L21/30604 , H01L21/3065 , H01L21/308 , H01L21/76224 , H01L29/0649
摘要： Among other things, one or more semiconductor arrangements comprising isolation trenches, and techniques for forming such isolation trenches are provided. A substrate comprises a front side surface and a backside surface. One or more devices are formed over the front side surface. A wet etch is performed to form a tapered portion of an isolation trench. A dry etch is performed to form a non-tapered portion of the isolation trench. Because both the wet etch and the dry etch are performed, etching time is reduced compared to merely using the dry etch due to the wet etch having a relatively faster etch rate than the dry etch. In an embodiment, the isolation trench provides isolation for a current leakage path associated with a device or other material formed over the front side surface. In an embodiment, metal is formed within the isolation trench for backside metallization.
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公开(公告)号：US20150001682A1
公开(公告)日：2015-01-01
申请号：US13930218
申请日：2013-06-28
发明人： Ming Chyi Liu , Sheng-de Liu , Chi-Ming Chen , Yuan-Tai Tseng , Chung-Yen Chou , Chia-Shiung Tsai
CPC分类号： H01L23/562 , H01L21/02002 , H01L2924/0002 , H01L2924/00
摘要： Among other things, one or more wafer edge protection structures and techniques for forming such wafer edge protection structures are provided. A substrate of a semiconductor wafer comprises an edge, such as a beveled wafer edge portion, that is susceptible to Epi growth which results in undesirable particle contamination of the semiconductor wafer. Accordingly, a wafer edge protection structure is formed over the beveled wafer edge portion. The wafer edge protection structure comprises an Epi growth resistant material, such as an amorphous material, a non-crystalline material, oxide, or other material. In this way, the wafer edge protection structure mitigates Epi growth on the beveled wafer edge portion, where the Epi growth increases a likelihood of particle contamination from cracking or peeling of an Epi film resulting from the Epi growth. The wafer edge protection structure thus mitigates at least some contamination of the wafer.
摘要翻译： 除此之外，还提供了一种或多种用于形成这种晶片边缘保护结构的晶片边缘保护结构和技术。 半导体晶片的衬底包括对Epi生长敏感的边缘，例如斜面晶片边缘部分，这导致半导体晶片的不期望的颗粒污染。 因此，在斜面晶片边缘部分上形成晶片边缘保护结构。 晶片边缘保护结构包括Epi生长抗性材料，例如非晶材料，非结晶材料，氧化物或其它材料。 以这种方式，晶片边缘保护结构减轻了斜面晶片边缘部分上的Epi生长，其中Epi生长增加了由Epi生长导致的Epi膜的颗粒污染破裂或剥离的可能性。 因此，晶片边缘保护结构至少减轻了晶片的一些污染。
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公开(公告)号：US10322930B2
公开(公告)日：2019-06-18
申请号：US15706916
申请日：2017-09-18
IPC分类号： B81C1/00
摘要： A semiconductor arrangement and methods of formation are provided. The semiconductor arrangement includes a micro-electro mechanical system (MEMS). A via opening is formed through a substrate, first dielectric layer and a first plug of the MEMS. The first plug comprises a first material, where the first material has an etch selectivity different than an etch selectivity of the first dielectric layer. The different etch selectivity of first plug allows the via opening to be formed relatively quickly and with a relatively high aspect ratio and desired a profile, as compared to forming the via opening without using the first plug.
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公开(公告)号：US09771256B2
公开(公告)日：2017-09-26
申请号：US14318667
申请日：2014-06-29
IPC分类号： H01L21/8242 , H01L23/48 , H01L21/3065 , H01L29/06 , H01L21/311 , H01L29/84 , B81C1/00
CPC分类号： B81C1/00238 , B81C2203/0792
摘要： A semiconductor arrangement and methods of formation are provided. The semiconductor arrangement includes a micro-electro mechanical system (MEMS). A via opening is formed through a substrate, first dielectric layer and a first plug of the MEMS. The first plug comprises a first material, where the first material has an etch selectivity different than an etch selectivity of the first dielectric layer. The different etch selectivity of first plug allows the via opening to be formed relatively quickly and with a relatively high aspect ratio and desired a profile, as compared to forming the via opening without using the first plug.
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公开(公告)号：US20150375992A1
公开(公告)日：2015-12-31
申请号：US14318667
申请日：2014-06-29
CPC分类号： B81C1/00238 , B81C2203/0792
摘要： A semiconductor arrangement and methods of formation are provided. The semiconductor arrangement includes a micro-electro mechanical system (MEMS). A via opening is formed through a substrate, first dielectric layer and a first plug of the MEMS. The first plug comprises a first material, where the first material has an etch selectivity different than an etch selectivity of the first dielectric layer. The different etch selectivity of first plug allows the via opening to be formed relatively quickly and with a relatively high aspect ratio and desired a profile, as compared to forming the via opening without using the first plug.
摘要翻译： 提供了半导体布置和形成方法。 半导体装置包括微机电系统（MEMS）。 通孔通过基底，第一介电层和MEMS的第一插塞形成。 第一插头包括第一材料，其中第一材料具有不同于第一介电层的蚀刻选择性的蚀刻选择性。 与在不使用第一插塞的情况下形成通孔开口相比，第一插塞的不同蚀刻选择性允许相对较快地形成通孔开口并且具有相对较高的纵横比和期望的轮廓。
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