公开(公告)号：US20230343711A1

公开(公告)日：2023-10-26

申请号：US18342335

申请日：2023-06-27

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Jheng-Hong Jiang ,  Chia-Wei Liu ,  Shing-Huang Wu

IPC分类号： H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L21/321 ,  H01L21/768

CPC分类号： H01L23/535 ,  H01L23/5283 ,  H01L23/53266 ,  H01L21/3212 ,  H01L21/76895 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76805

摘要： A device structure may include an interconnect-level dielectric material layer located over a substrate, a first metal interconnect structure embedded in the interconnect-level dielectric material layer and including a first metallic barrier liner and a first metallic fill material portion, and an overlying dielectric material layer. An opening in the overlying dielectric material layer may be formed entirely within an area of the first metallic barrier layer and outside the area of the first metallic fill material portion to reduce plasma damage. A second metal interconnect structure contacting a top surface of the first metallic barrier liner may be formed in the opening. An entirety of a top surface the first metallic fill material portion contacts a bottom surface of the overlying dielectric material layer.

公开(公告)号：US12027431B2

公开(公告)日：2024-07-02

申请号：US17348858

申请日：2021-06-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

发明人： Jheng-Hong Jiang ,  Shing-Huang Wu ,  Chia-Wei Liu

IPC分类号： H01L23/00 ,  H01L21/66 ,  H01L21/768

CPC分类号： H01L22/32 ,  H01L21/76877 ,  H01L22/14

摘要： A method of forming a semiconductor structure includes forming a first conductive contact in a first dielectric layer coupled to a first device and forming a second conductive contact in the first dielectric layer coupled to a second device. A first trench is formed in the first dielectric layer having a first depth and exposing at least a portion of the first conductive contact. A second trench is formed in the first dielectric layer having a second depth different than the first depth and exposing at least a portion of the second conductive contact. A first conductive layer is formed in the first trench and the second trench. A second dielectric layer is formed in the first trench and the second trench over the first conductive layer.

公开(公告)号：US12131915B2

公开(公告)日：2024-10-29

申请号：US18325905

申请日：2023-05-30

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Jheng-Hong Jiang ,  Chia-Wei Liu ,  Shing-Huang Wu

IPC分类号： H01L21/321 ,  C22C21/12 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/3212 ,  C22C21/12 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53219 ,  H01L23/53223

摘要： A cavity may be formed in a dielectric material layer overlying a substrate. A layer stack including a metallic barrier liner, a metallic fill material layer, and a metallic capping material may be deposited in the cavity and over the dielectric material layer. Portions of the layer stack located above a horizontal plane including a top surface of the dielectric material layer may be removed. A contiguous set of remaining material portions of the layer stack includes a metal interconnect structure that is free of a pitted surface.

公开(公告)号：US11848291B2

公开(公告)日：2023-12-19

申请号：US17470174

申请日：2021-09-09

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Jheng-Hong Jiang ,  Shing-Huang Wu ,  Chia-Wei Liu

IPC分类号： H01L23/66 ,  H01L23/522 ,  H01L49/02 ,  H01L21/768

CPC分类号： H01L23/66 ,  H01L21/76849 ,  H01L23/5226 ,  H01L28/90 ,  H01L2223/6616 ,  H01L2223/6672 ,  H01L2223/6688

摘要： Devices and methods of manufacture for a graduated, “step-like,” semiconductor structure having two or more resonator trenches. A semiconductor structure may comprise a first resonator and a second resonator. The first resonator comprising a first metallic resonance layer and a capping plate having a bottom surface that is a first distance from a distal end of the first metallic resonance layer 128. The second resonator comprising a second metallic resonance layer and the capping plate, in which the bottom surface is a second distance from a from a distal end of the second metallic resonance layer 128b, and in which first distance is different from the second distance.

公开(公告)号：US20230298903A1

公开(公告)日：2023-09-21

申请号：US18325905

申请日：2023-05-30

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Jheng-Hong Jiang ,  Chia-Wei Liu ,  Shing-Huang Wu

IPC分类号： H01L21/321 ,  H01L23/522 ,  H01L23/532 ,  C22C21/12 ,  H01L21/768

CPC分类号： H01L21/3212 ,  H01L23/5226 ,  H01L23/53219 ,  H01L23/53223 ,  C22C21/12 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76802

摘要： A cavity may be formed in a dielectric material layer overlying a substrate. A layer stack including a metallic barrier liner, a metallic fill material layer, and a metallic capping material may be deposited in the cavity and over the dielectric material layer. Portions of the layer stack located above a horizontal plane including a top surface of the dielectric material layer may be removed. A contiguous set of remaining material portions of the layer stack includes a metal interconnect structure that is free of a pitted surface.

公开(公告)号：US11728272B2

公开(公告)日：2023-08-15

申请号：US17218435

申请日：2021-03-31

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Jheng-Hong Jiang ,  Shing-Huang Wu ,  Chia-Wei Liu

IPC分类号： H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L21/321 ,  H01L21/768

CPC分类号： H01L23/535 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76895 ,  H01L23/5283 ,  H01L23/53266

摘要： A device structure may include an interconnect-level dielectric material layer located over a substrate, a first metal interconnect structure embedded in the interconnect-level dielectric material layer and including a first metallic barrier liner and a first metallic fill material portion, and an overlying dielectric material layer. An opening in the overlying dielectric material layer may be formed entirely within an area of the first metallic barrier layer and outside the area of the first metallic fill material portion to reduce plasma damage. A second metal interconnect structure contacting a top surface of the first metallic barrier liner may be formed in the opening. An entirety of a top surface the first metallic fill material portion contacts a bottom surface of the overlying dielectric material layer.

公开(公告)号：US11705340B2

公开(公告)日：2023-07-18

申请号：US17218471

申请日：2021-03-31

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Jheng-Hong Jiang ,  Shing-Huang Wu ,  Chia-Wei Liu

IPC分类号： H01L21/321 ,  H01L23/522 ,  H01L23/532 ,  C22C21/12 ,  H01L21/768

CPC分类号： H01L21/3212 ,  C22C21/12 ,  H01L21/7684 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53219 ,  H01L23/53223

摘要： A cavity may be formed in a dielectric material layer overlying a substrate. A layer stack including a metallic barrier liner, a metallic fill material layer, and a metallic capping material may be deposited in the cavity and over the dielectric material layer. Portions of the layer stack located above a horizontal plane including a top surface of the dielectric material layer may be removed. A contiguous set of remaining material portions of the layer stack includes a metal interconnect structure that is free of a pitted surface.

公开(公告)号：US20220301951A1

公开(公告)日：2022-09-22

申请号：US17348858

申请日：2021-06-16

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Jheng-Hong Jiang ,  Shing-Huang Wu ,  Chia-Wei Liu

IPC分类号： H01L21/66 ,  H01L21/768

摘要： A method of forming a semiconductor structure includes forming a first conductive contact in a first dielectric layer coupled to a first device and forming a second conductive contact in the first dielectric layer coupled to a second device. A first trench is formed in the first dielectric layer having a first depth and exposing at least a portion of the first conductive contact. A second trench is formed in the first dielectric layer having a second depth different than the first depth and exposing at least a portion of the second conductive contact. A first conductive layer is formed in the first trench and the second trench. A second dielectric layer is formed in the first trench and the second trench over the first conductive layer.