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107 条记录 (耗时 0.033 秒)

    Automatic gain control apparatus
    2.
    发明授权
    Automatic gain control apparatus 失效
    自动增益控制装置

    公开(公告)号：US06934522B2

    公开(公告)日：2005-08-23

    申请号：US09886377

    申请日：2001-06-22

    申请人： Takaaki Konishi ,  Hiroshi Azakami ,  Kazuya Ueda ,  Naoya Tokunaga ,  Hisaya Kato ,  Hiroaki Ozeki

    发明人： Takaaki Konishi ,  Hiroshi Azakami ,  Kazuya Ueda ,  Naoya Tokunaga ,  Hisaya Kato ,  Hiroaki Ozeki

    IPC分类号： H03G3/20 ,  H03G1/04 ,  H04B1/28 ,  H04B1/06

    CPC分类号： H03G1/04 ,  H04B1/28

    摘要： In an automatic gain control amplifier, an RF automatic gain controller controls the gain of a radio frequency signal. A frequency converter frequency-converts the radio frequency signal into an intermediate frequency signal. An IF automatic gain controller controls the gain of the intermediate frequency. A level detector detects a signal level of the gain-controlled intermediate frequency signal, and generates a level signal. An automatic gain control signal generator separately controls, based the level signal, the RF automatic gain controller and the IF automatic gain controller.

    摘要翻译： 在自动增益控制放大器中，RF自动增益控制器控制射频信号的增益。 变频器将射频信号频率转换成中频信号。 中频自动增益控制器控制中频增益。 电平检测器检测增益控制中频信号的信号电平，并产生电平信号。 自动增益控制信号发生器基于电平信号单独控制RF自动增益控制器和IF自动增益控制器。

    Automatic gain control for digital demodulation apparatus
    3.
    发明授权
    Automatic gain control for digital demodulation apparatus 失效
    数字解调装置的自动增益控制

    公开(公告)号：US07054395B2

    公开(公告)日：2006-05-30

    申请号：US09853682

    申请日：2001-05-14

    申请人： Hiroshi Azakami ,  Takaaki Konishi ,  Hisaya Kato ,  Naoya Tokunaga ,  Hiroaki Ozeki ,  Kazuya Ueda

    发明人： Hiroshi Azakami ,  Takaaki Konishi ,  Hisaya Kato ,  Naoya Tokunaga ,  Hiroaki Ozeki ,  Kazuya Ueda

    IPC分类号： H04L27/08

    CPC分类号： H03G3/3089

    摘要： A digital demodulation apparatus automatically controls gain based on a state of receiving a digital modulated signal. The digital demodulation apparatus amplifies a digital modulated signal wave received through the air with the gain automatically controlled so as to have a predetermined amplitude. In the digital demodulation apparatus, a receive level variation detector detects receive level variation, an amount of noise components of the received digital signal wave. A gain controller 15 controls the gain with a receive level variation adaptive control signal based on the detected receive level variation, the amount of noise components.

    摘要翻译： 数字解调装置根据接收数字调制信号的状态自动控制增益。 数字解调装置以自动控制的增益放大通过空气接收的数字调制信号波，以具有预定的幅度。 在数字解调装置中，接收电平变化检测器检测接收电平变化，接收的数字信号波的噪声分量的量。 增益控制器15基于检测到的接收电平变化，噪声分量的量，利用接收电平变化自适应控制信号来控制增益。

    Synchronization detection apparatus
    4.
    发明授权
    Synchronization detection apparatus 失效
    同步检测装置

    公开(公告)号：US07133481B2

    公开(公告)日：2006-11-07

    申请号：US10311638

    申请日：2002-04-05

    申请人： Hiroshi Azakami ,  Takaaki Konishi ,  Hisaya Kato ,  Naoya Tokunaga ,  Kazuaki Suzuki ,  Kazuya Ueda

    发明人： Hiroshi Azakami ,  Takaaki Konishi ,  Hisaya Kato ,  Naoya Tokunaga ,  Kazuaki Suzuki ,  Kazuya Ueda

    IPC分类号： H04L7/00

    CPC分类号： H04N5/211 ,  H04H40/18 ,  H04L7/042 ,  H04L7/06 ,  H04L27/02 ,  H04N5/08

    摘要： An input signal DT contains a segment synchronization signal compliant with the ATSC standard. A clock multiplication section 111 multiplies a clock CK. A switchable sampling section 112 selects a sample point from among a plurality of timing points that are defined by the multiplied clock, and samples the input signal DT at the selected sample point. Moreover, the switchable sampling section 112 switches sample points from one to another in a synchronization-unestablished state. Once the segment synchronization is established, a synchronization detection device may maintain a synchronization-established state until the field synchronization detection fails, or the synchronization detection device may output a synchronization detection signal after shifting it in the time direction based on a bit error rate RT of the input signal.

    摘要翻译： 输入信号DT包含符合ATSC标准的片段同步信号。 时钟倍增部分111将时钟CK相乘。 可切换取样部112从由倍增时钟定义的多个定时点中选择采样点，并对选择的采样点对输入信号DT进行采样。 此外，可切换采样部112在同步未建立状态下将采样点从一个切换到另一个。 一旦段同步建立，同步检测装置可以保持同步建立状态，直到现场同步检测失败，或者同步检测装置可以在基于位错误率RT在时间方向上移动同步检测信号之后输出同步检测信号 的输入信号。

    Synchronizing signal detecting device
    5.
    发明授权
    Synchronizing signal detecting device 有权
    同步信号检测装置

    公开(公告)号：US6069667A

    公开(公告)日：2000-05-30

    申请号：US171079

    申请日：1998-10-13

    申请人： Kazuya Ueda ,  Takaaki Konishi

    发明人： Kazuya Ueda ,  Takaaki Konishi

    IPC分类号： H04J3/06 ,  H04L7/08 ,  H04N5/08 ,  H04L7/00 ,  H04N5/10

    CPC分类号： H04N5/08

    摘要： In a Sync signal detection circuit for detecting a Sync signal included in a television signal transmitted in a digital mode, pattern check means 2 checks a pattern of a Sync signal which is super imposed on a series of input data with a reference pattern. Based on a check result, Sync detection determination means 5 outputs a Sync detected signal or a Sync non-detected signal. Sync detection initialization means is further provided to this detection circuit for outputting forcibly a Sync non-detected signal when a signal of a series of input data is switched over. As a result, a Sync signal can be detected within a shorter period than the conventional circuit structure.

    摘要翻译： PCT No.PCT / JP98 / 00538 Sec。 371日期：1998年10月13日 102（e）1998年10月13日PCT PCT 1998年2月10日PCT公布。 第WO98 / 36558号公报 日期1998年8月20日在同步信号检测电路中，检测包含在以数字模式发送的电视信号中的同步信号，模式检查装置2检查超级施加在一系列输入数据上的同步信号的模式， 参考模式。 基于检查结果，同步检测确定装置5输出同步检测信号或同步未检测信号。 当一系列输入数据的信号被切换时，同步检测初始化装置还被提供给该检测电路，用于强制输出同步未检测信号。 结果，可以在比传统电路结构更短的周期内检测同步信号。

    Digital broadcast receiving apparatus
    6.
    发明授权
    Digital broadcast receiving apparatus 失效
    数字广播接收装置

    公开(公告)号：US07302021B2

    公开(公告)日：2007-11-27

    申请号：US09878427

    申请日：2001-06-12

    申请人： Takaaki Konishi ,  Hiroshi Azakami ,  Kazuya Ueda ,  Naoya Tokunaga

    发明人： Takaaki Konishi ,  Hiroshi Azakami ,  Kazuya Ueda ,  Naoya Tokunaga

    IPC分类号： H04L27/08

    CPC分类号： H04N5/4446 ,  H03G3/3068 ,  H03G3/3089 ,  H04H40/18 ,  H04N5/4401 ,  H04N5/50 ,  H04N5/52 ,  H04N21/42607

    摘要： In a digital broadcast receiving apparatus for amplifying a received modulated digital signal wave with automatically adjusted gain and demodulating the modulated signal wave to a digital signal, a tuner frequency-converts the modulated digital signal wave to generate a first modulated signal. A first automatic gain control amplification unit controls gain of the tuner to make a level of the first modulated signal at a first predetermined level. An A/D converter converts the first modulated signal into a second modulated signal. A demodulator demodulates the second modulated signal to generate a first demodulated digital signal. A second automatic gain control amplifier generates a second demodulated digital signal where frequency fluctuations included in the digital modulated wave are eliminated.

    摘要翻译： 在一种数字广播接收装置中，用于利用自动调节增益放大接收到的调制数字信号波并将调制信号波解调为数字信号，调谐器对调制数字信号波进行频率转换以产生第一调制信号。 第一自动增益控制放大单元控制调谐器的增益使第一调制信号的电平达到第一预定电平。 A / D转换器将第一调制信号转换成第二调制信号。 解调器解调第二调制信号以产生第一解调数字信号。 第二自动增益控制放大器产生第二解调数字信号，其中消除了数字调制波中包括的频率波动。

    VSB receiver
    7.
    发明授权
    VSB receiver 有权
    VSB接收机

    公开(公告)号：US06671002B1

    公开(公告)日：2003-12-30

    申请号：US09555150

    申请日：2000-08-07

    申请人： Takaaki Konishi ,  Kazuya Ueda ,  Hiroshi Azakami

    发明人： Takaaki Konishi ,  Kazuya Ueda ,  Hiroshi Azakami

    IPC分类号： H04N544

    CPC分类号： H04N5/4401 ,  H03G3/3052 ,  H03G3/3078 ,  H03L7/107 ,  H04L27/08 ,  H04N5/211 ,  H04N5/52

    摘要： The loop gain of an AGC circuit 7 and the loop gain of a clock regenerating circuit 6 are increased (the gain of an amplifier is increased, or the band of a loop filter is widened) until a synchronizing signal (a segment synchronizing signal or a field synchronizing signal) is detected. The loop gain of the AGC circuit 7 and the loop gain of the clock regenerating circuit 6 are decreased (the gain of the amplifier is decreased, or the band of the loop filter is narrowed) after the synchronizing signal is detected. Consequently, it is possible to make a reduction of a time period required until convergence processing is completed in the AGC circuit and the clock regenerating circuit compatible with an improvement of a ghost disturbance removal performance and accurate clock regeneration.

    摘要翻译： AGC电路7的环路增益和时钟再生电路6的环路增益增加（放大器的增益增加或环路滤波器的频带被加宽），直到同步信号（段同步信号或 场同步信号）。 在检测到同步信号之后，AGC电路7的环路增益和时钟再生电路6的环路增益被减小（放大器的增益减小或环路滤波器的频带变窄）。因此， 可以减少在AGC电路和时钟再生电路中的会聚处理完成所需的时间段，其与改善重影干扰去除性能和精确的时钟再生相兼容。

    Liquid crystal display
    9.
    发明授权
    Liquid crystal display 有权
    液晶显示器

    公开(公告)号：US08427610B2

    公开(公告)日：2013-04-23

    申请号：US13113539

    申请日：2011-05-23

    申请人： Kazuya Ueda ,  Tsuyoshi Kamada ,  Hidefumi Yoshida ,  Yoshio Koike ,  Kenji Okamoto ,  Yuichi Inoue ,  Seiji Tanuma

    发明人： Kazuya Ueda ,  Tsuyoshi Kamada ,  Hidefumi Yoshida ,  Yoshio Koike ,  Kenji Okamoto ,  Yuichi Inoue ,  Seiji Tanuma

    IPC分类号： G02F1/1337 ,  G02F1/133

    CPC分类号： G02F1/133707 ,  C09K19/02 ,  C09K19/56 ,  G02F1/133371 ,  G02F1/133753 ,  G02F1/1393

    摘要： A liquid crystal display device includes a pair of substrates provided opposite to each other, a common electrode provided on one of the pair of substrates, and a pixel electrode provided on the other of the pair of substrates. A vertical alignment type liquid crystal is sealed between the pair of substrates. An alignment film is polymerizable upon irradiation of UV, and is obtained by polymerizing substantially the entire alignment film with a voltage applied between the electrodes after the liquid crystal is sealed between the substrates. A pixel region has areas whose electro-optical characteristics are different from each other because of a difference between applied voltages at the time of polymerization.

    摘要翻译： 液晶显示装置包括彼此相对设置的一对基板，设置在一对基板中的一个基板上的公共电极和设置在该对基板中的另一个基板上的像素电极。 在一对基板之间密封垂直取向型液晶。 取向膜在照射紫外线时是可聚合的，并且通过在液晶被密封在基板之后，在施加在电极之间的电压基本上聚合整个取向膜而获得。 像素区域由于聚合时的施加电压的差异而具有电光特性彼此不同的区域。