公开(公告)号：USRE36751E

公开(公告)日：2000-06-27

申请号：US430802

申请日：1995-04-26

申请人： Takahiko Kozaki ,  Junichirou Yanagi ,  Kiyoshi Aiki ,  Yutaka Ito ,  Kaoru Aoki ,  Shinobu Gohara

发明人： Takahiko Kozaki ,  Junichirou Yanagi ,  Kiyoshi Aiki ,  Yutaka Ito ,  Kaoru Aoki ,  Shinobu Gohara

IPC分类号： H04J3/24 ,  H04L12/56 ,  H04Q11/04

CPC分类号： H04Q11/0478 ,  H04J3/247 ,  H04L12/5601 ,  H04L12/5602 ,  H04L45/04 ,  H04L49/108 ,  H04L49/256 ,  H04L49/3081 ,  H04L2012/5627 ,  H04L2012/5651 ,  H04L2012/5652 ,  H04L2012/5672 ,  H04L2012/5681

摘要： An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.

摘要翻译： ATM交换系统包括具有多个输入端口和具有相同信元传输速率的多个输出端口的开关单元，以及多路复用器，用于将从至少两个输出端口输出的单元列复用为单个单元列，并输出该单元 训练到高速输出线（和/或解复用器，用于从输出端口多路复用到多个单元列，并将单元列输出到多个低速输出线）。 开关单元包括缓冲存储器，用于临时存储从输入端口输入的单元，同时形成用于每个单元将被输出到的每个输出线的队列链;解复用器，用于将从缓冲存储器读取的单元在输出端口之中分配 以及缓冲存储器控制电路，用于通过共享缓冲存储器来控制单元的写入和读取操作。 缓冲存储器控制电路具有用于输出要从共享缓冲存储器读取的单元被输出的输出行的标识符的控制表装置，并且从由控制器输出的输出行标识符指定的链中读取单元 表装置。

公开(公告)号：US5799014A

公开(公告)日：1998-08-25

申请号：US306978

申请日：1994-09-16

申请人： Takahiko Kozaki ,  Junichirou Yanagi ,  Kiyoshi Aiki ,  Yutaka Ito ,  Kaoru Aoki ,  Shinobu Gohara

发明人： Takahiko Kozaki ,  Junichirou Yanagi ,  Kiyoshi Aiki ,  Yutaka Ito ,  Kaoru Aoki ,  Shinobu Gohara

IPC分类号： H04J3/24 ,  H04L12/56 ,  H04Q11/04

CPC分类号： H04L12/5601 ,  H04J3/247 ,  H04L12/5602 ,  H04L45/04 ,  H04L49/108 ,  H04L49/203 ,  H04L49/255 ,  H04L49/256 ,  H04L49/3081 ,  H04Q11/0478 ,  H04L2012/5627 ,  H04L2012/5631 ,  H04L2012/5638 ,  H04L2012/5649 ,  H04L2012/565 ,  H04L2012/5651 ,  H04L2012/5652 ,  H04L2012/5672 ,  H04L2012/5679 ,  H04L2012/568 ,  H04L2012/5681 ,  H04L2012/5682

摘要： An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.

公开(公告)号：US5710770A

公开(公告)日：1998-01-20

申请号：US462532

申请日：1995-06-05

申请人： Takahiko Kozaki ,  Junichirou Yanagi ,  Kiyoshi Aiki ,  Yutaka Ito ,  Kaoru Aoki ,  Shinobu Gohara

发明人： Takahiko Kozaki ,  Junichirou Yanagi ,  Kiyoshi Aiki ,  Yutaka Ito ,  Kaoru Aoki ,  Shinobu Gohara

IPC分类号： H04J3/24 ,  H04L12/56 ,  H04Q11/04

CPC分类号： H04L12/5601 ,  H04J3/247 ,  H04L12/5602 ,  H04L45/04 ,  H04L49/108 ,  H04L49/203 ,  H04L49/255 ,  H04L49/256 ,  H04L49/3081 ,  H04Q11/0478 ,  H04L2012/5627 ,  H04L2012/5631 ,  H04L2012/5638 ,  H04L2012/5649 ,  H04L2012/565 ,  H04L2012/5651 ,  H04L2012/5652 ,  H04L2012/5672 ,  H04L2012/5679 ,  H04L2012/568 ,  H04L2012/5681 ,  H04L2012/5682

摘要： An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.

公开(公告)号：US06463057B1

公开(公告)日：2002-10-08

申请号：US09714947

申请日：2000-11-20

申请人： Takahiko Kozaki ,  Junichirou Yanagi ,  Kiyoshi Aiki ,  Yutaka Ito ,  Kaoru Aoki ,  Shinobu Gohara

发明人： Takahiko Kozaki ,  Junichirou Yanagi ,  Kiyoshi Aiki ,  Yutaka Ito ,  Kaoru Aoki ,  Shinobu Gohara

IPC分类号： H04L1256

CPC分类号： H04L12/5601 ,  H04J3/247 ,  H04L12/5602 ,  H04L45/04 ,  H04L49/108 ,  H04L49/203 ,  H04L49/255 ,  H04L49/256 ,  H04L49/3081 ,  H04L2012/5627 ,  H04L2012/5631 ,  H04L2012/5638 ,  H04L2012/5649 ,  H04L2012/565 ,  H04L2012/5651 ,  H04L2012/5652 ,  H04L2012/5672 ,  H04L2012/5679 ,  H04L2012/568 ,  H04L2012/5681 ,  H04L2012/5682 ,  H04Q11/0478

摘要： An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.

摘要翻译： ATM交换系统包括具有多个输入端口和具有相同信元传输速率的多个输出端口的开关单元，以及多路复用器，用于将从至少两个输出端口输出的单元列复用为单个单元列，并输出该单元 训练到高速输出线（和/或解复用器，用于从输出端口多路复用到多个单元列，并将单元列输出到多个低速输出线）。 开关单元包括缓冲存储器，用于临时存储从输入端口输入的单元，同时形成用于每个单元将被输出到的每个输出线的队列链;解复用器，用于将从缓冲存储器读取的单元在输出端口之中分配 以及缓冲存储器控制电路，用于通过共享缓冲存储器来控制单元的写入和读取操作。 缓冲存储器控制电路具有用于输出要从共享缓冲存储器读取的单元被输出的输出行的标识符的控制表装置，并且从由控制器输出的输出行标识符指定的链中读取单元 表装置。

公开(公告)号：US06396831B1

公开(公告)日：2002-05-28

申请号：US09715104

申请日：2000-11-20

申请人： Takahiko Kozaki ,  Junichirou Yanagi ,  Kiyoshi Aiki ,  Yutaka Ito ,  Kaoru Aoki ,  Shinobu Gohara

发明人： Takahiko Kozaki ,  Junichirou Yanagi ,  Kiyoshi Aiki ,  Yutaka Ito ,  Kaoru Aoki ,  Shinobu Gohara

IPC分类号： H04L1256

CPC分类号： H04L12/5601 ,  H04J3/247 ,  H04L12/5602 ,  H04L45/04 ,  H04L49/108 ,  H04L49/203 ,  H04L49/255 ,  H04L49/256 ,  H04L49/3081 ,  H04L2012/5627 ,  H04L2012/5631 ,  H04L2012/5638 ,  H04L2012/5649 ,  H04L2012/565 ,  H04L2012/5651 ,  H04L2012/5652 ,  H04L2012/5672 ,  H04L2012/5679 ,  H04L2012/568 ,  H04L2012/5681 ,  H04L2012/5682 ,  H04Q11/0478

摘要： An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.

公开(公告)号：US06339596B1

公开(公告)日：2002-01-15

申请号：US08906909

申请日：1997-08-06

申请人： Takahiko Kozaki ,  Junichirou Yanagi ,  Kiyoshi Aiki ,  Yutaka Ito ,  Kaoru Aoki ,  Shinobu Gohara

发明人： Takahiko Kozaki ,  Junichirou Yanagi ,  Kiyoshi Aiki ,  Yutaka Ito ,  Kaoru Aoki ,  Shinobu Gohara

IPC分类号： H04L1256

CPC分类号： H04L12/5601 ,  H04J3/247 ,  H04L12/5602 ,  H04L45/04 ,  H04L49/108 ,  H04L49/203 ,  H04L49/255 ,  H04L49/256 ,  H04L49/3081 ,  H04L2012/5627 ,  H04L2012/5631 ,  H04L2012/5638 ,  H04L2012/5649 ,  H04L2012/565 ,  H04L2012/5651 ,  H04L2012/5652 ,  H04L2012/5672 ,  H04L2012/5679 ,  H04L2012/568 ,  H04L2012/5681 ,  H04L2012/5682 ,  H04Q11/0478

摘要： An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.

公开(公告)号：US06330240B1

公开(公告)日：2001-12-11

申请号：US09351125

申请日：1999-07-12

申请人： Takahiko Kozaki ,  Junichirou Yanagi ,  Kiyoshi Aiki ,  Yutaka Ito ,  Kaoru Aoki

发明人： Takahiko Kozaki ,  Junichirou Yanagi ,  Kiyoshi Aiki ,  Yutaka Ito ,  Kaoru Aoki

IPC分类号： H04L1256

CPC分类号： H04L12/5601 ,  H04J3/247 ,  H04L12/5602 ,  H04L45/04 ,  H04L49/108 ,  H04L49/203 ,  H04L49/255 ,  H04L2012/565 ,  H04L2012/5652 ,  H04L2012/5672 ,  H04L2012/5681 ,  H04Q11/0478

摘要： An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.

摘要翻译： ATM交换系统包括具有多个输入端口和具有相同信元传输速率的多个输出端口的开关单元，以及多路复用器，用于将从至少两个输出端口输出的单元列复用为单个单元列，并输出该单元 训练到高速输出线（和/或解复用器，用于从输出端口多路复用到多个单元列，并将单元列输出到多个低速输出线）。 开关单元包括缓冲存储器，用于临时存储从输入端口输入的单元，同时形成用于每个单元将被输出到的每个输出线的队列链;解复用器，用于将从缓冲存储器读取的单元在输出端口之中分配 以及缓冲存储器控制电路，用于通过共享缓冲存储器来控制单元的写入和读取操作。 缓冲存储器控制电路具有用于输出要从共享缓冲存储器读取的单元被输出的输出行的标识符的控制表装置，并且从由控制器输出的输出行标识符指定的链中读取单元 表装置。

公开(公告)号：US5365519A

公开(公告)日：1994-11-15

申请号：US845668

申请日：1992-03-04

申请人： Takahiko Kozaki ,  Junichirou Yanagi ,  Kiyoshi Aiki ,  Yutaka Ito ,  Kaoru Aoki

发明人： Takahiko Kozaki ,  Junichirou Yanagi ,  Kiyoshi Aiki ,  Yutaka Ito ,  Kaoru Aoki

IPC分类号： H04J3/24 ,  H04L12/56 ,  H04Q11/04

CPC分类号： H04L12/5601 ,  H04J3/247 ,  H04L12/5602 ,  H04L45/04 ,  H04L49/108 ,  H04L49/203 ,  H04L49/255 ,  H04L49/256 ,  H04L49/3081 ,  H04Q11/0478 ,  H04L2012/5627 ,  H04L2012/5631 ,  H04L2012/5638 ,  H04L2012/5649 ,  H04L2012/565 ,  H04L2012/5651 ,  H04L2012/5652 ,  H04L2012/5672 ,  H04L2012/5679 ,  H04L2012/568 ,  H04L2012/5681 ,  H04L2012/5682

摘要： An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.

摘要翻译： ATM交换系统包括具有多个输入端口和具有相同信元传输速率的多个输出端口的开关单元，以及多路复用器，用于将从至少两个输出端口输出的单元列复用为单个单元列，并输出该单元 训练到高速输出线（和/或解复用器，用于从输出端口多路复用到多个单元列，并将单元列输出到多个低速输出线）。 开关单元包括缓冲存储器，用于临时存储从输入端口输入的单元，同时形成用于每个单元将被输出到的每个输出线的队列链;解复用器，用于将从缓冲存储器读取的单元在输出端口之中分配 以及缓冲存储器控制电路，用于通过共享缓冲存储器来控制单元的写入和读取操作。 缓冲存储器控制电路具有用于输出要从共享缓冲存储器读取的单元被输出的输出行的标识符的控制表装置，并且从由控制器输出的输出行标识符指定的链中读取单元 表装置。

公开(公告)号：US5410540A

公开(公告)日：1995-04-25

申请号：US132999

申请日：1993-10-07

申请人： Kiyoshi Aiki ,  Takahiko Kozaki ,  Noboru Endo ,  Haruo Shibata

发明人： Kiyoshi Aiki ,  Takahiko Kozaki ,  Noboru Endo ,  Haruo Shibata

IPC分类号： H04Q3/52 ,  H04L12/18 ,  H04L12/931 ,  H04Q11/04

CPC分类号： H04L12/5601 ,  H04L49/108 ,  H04L49/203 ,  H04L49/309 ,  H04L2012/5672

摘要： In a shared-buffer-type ATM switch including a multiplexer, a shared buffer memory, a demultiplexer, a buffer memory controller, a cell copy section is disposed between the multiplexer and the memory. The copy section produces a plurality of copies of a broadcast cell according to information of a copy information table and adds associate routing information to each copied cell so as to write the cells in the memory. In response to an indication from an output counter, the cells are read from the memory to be distributed to output ports, thereby implementing a broadcast function.

摘要翻译： 在包括多路复用器，共享缓冲存储器，解复用器，缓冲存储器控制器的共享缓冲器型ATM交换机中，单元复制部分设置在多路复用器和存储器之间。 复制部分根据复制信息表的信息产生广播小区的多个副本，并将关联路由信息添加到每个复制的小区，以便将单元写入存储器。 响应于来自输出计数器的指示，从存储器读取单元以分配到输出端口，从而实现广播功能。

公开(公告)号：US07626498B2

公开(公告)日：2009-12-01

申请号：US11208632

申请日：2005-08-23

申请人： Kiyoshi Aiki ,  Hiroyuki Kuriyama ,  Shunzo Yamashita ,  Takanori Shimura

发明人： Kiyoshi Aiki ,  Hiroyuki Kuriyama ,  Shunzo Yamashita ,  Takanori Shimura

IPC分类号： G08B1/08

CPC分类号： H01Q1/273 ,  H01Q9/0485

摘要： To secure a stable radio-communication performance in a sensor node, the sensor node with a radio-communication circuit and a sensor, for transmitting data measured by the sensor through radio-communication, includes a first board BO2 on which an antenna ANT1 connected to the radio-communication circuit is placed, a case CASE1 containing the first board BO2, and a band that is attached to the case CASE1 so as to fix the case CASE1 to the skin. The antenna ANT1 is placed in an upper portion of the case CASE1, which corresponds to a 12 o'clock direction of a wristwatch.

摘要翻译： 为了确保传感器节点中的稳定的无线电通信性能，具有用于通过无线电通信传输由传感器测量的数据的无线电通信电路和传感器的传感器节点包括第一板B02，其上连接有天线ANT1 放置无线电通信电路，包含第一板BO2的壳体CASE1和附接到壳体CASE1的带，以将壳体CASE1固定到皮肤上。 天线ANT1被放置在壳体CASE1的上部，其对应于手表的12点钟方向。