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1.发明申请MEMORY CONTROL DEVICE, SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM, AND MEMORY CONTROL METHOD 有权存储器控制装置，半导体存储器件，存储器系统和存储器控制方法公开(公告)号：US20120023338A1
公开(公告)日：2012-01-26
申请号：US13257644
申请日：2010-04-05
IPC分类号： G06F12/14
CPC分类号： G06F21/72 , G06F2221/2105
摘要： A technique for improving data security is provided. To be specific, in a memory system including an information processing apparatus and a semiconductor memory device, the semiconductor memory device has an interface section that transmits, to the information processing apparatus, data read out from a memory core according to a plurality of communication protocols having different signal transmission/reception methods. Based on a switch command inputted from the information processing apparatus, a communication protocol selection section inputs, to the interface section, a selection signal for selecting a particular communication protocol from the plurality of communication protocols.
摘要翻译： 提供了一种提高数据安全性的技术。 具体地说，在包括信息处理装置和半导体存储装置的存储器系统中，半导体存储装置具有接口部，该接口部根据多个通信协议向信息处理装置发送从存储器核心读出的数据 具有不同的信号发送/接收方法。 基于从信息处理装置输入的切换命令，通信协议选择部将从多个通信协议中选择特定通信协议的选择信号输入到接口部。
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2.发明授权Memory control device, semiconductor memory device, memory system, and memory control method 有权存储器控制装置，半导体存储器件，存储器系统和存储器控制方法公开(公告)号：US09003202B2
公开(公告)日：2015-04-07
申请号：US13257644
申请日：2010-04-05
CPC分类号： G06F21/72 , G06F2221/2105
摘要： A technique for improving data security is provided. To be specific, in a memory system including an information processing apparatus and a semiconductor memory device, the semiconductor memory device has an interface section that transmits, to the information processing apparatus, data read out from a memory core according to a plurality of communication protocols having different signal transmission/reception methods. Based on a switch command inputted from the information processing apparatus, a communication protocol selection section inputs, to the interface section, a selection signal for selecting a particular communication protocol from the plurality of communication protocols.
摘要翻译： 提供了一种提高数据安全性的技术。 具体地说，在包括信息处理装置和半导体存储装置的存储器系统中，半导体存储装置具有接口部，该接口部根据多个通信协议向信息处理装置发送从存储器核心读出的数据 具有不同的信号发送/接收方法。 基于从信息处理装置输入的切换命令，通信协议选择部将从多个通信协议中选择特定通信协议的选择信号输入到接口部。
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3.发明申请MEMORY CONTROLLER, MEMORY CONTROL DEVICE MEMORY DEVICE, MEMORY INFORMATION PROTECTION SYSTEM, CONTROL METHOD FOR MEMORY CONTROL DEVICE, AND CONTROL METHOD FOR MEMORY DEVICE 有权存储器控制器，存储器控制器件存储器件，存储器信息保护系统，用于存储器控制器件的控制方法和用于存储器件的控制方法公开(公告)号：US20120008772A1
公开(公告)日：2012-01-12
申请号：US13257680
申请日：2010-04-05
IPC分类号： H04L9/00
CPC分类号： H04L9/0869 , G06F21/79 , G06F21/80 , H04L9/06 , H04L9/0894 , H04L2209/12
摘要： A technique allowing an improvement in the confidentiality of information stored in a memory device. A memory controller includes a key generation part that newly generates key information for use in encryption and decryption of information at every predetermined timing, and a data conversion circuit that encrypts information to be outputted to a memory device based on the information and decrypts encrypted information inputted from the memory device based on the key information. In the data conversion circuit, each time the key generation part generates new key information, key information is updated so as to set the new key information as the key information.
摘要翻译： 一种允许改善存储在存储装置中的信息的机密性的技术。 存储器控制器包括：新产生用于在每个预定定时对信息进行加密和解密的密钥信息的密钥生成部件;以及数据转换电路，其根据该信息对输出到存储器件的信息进行加密，并解密输入的加密信息 从存储设备基于密钥信息。 在数据转换电路中，每当密钥生成部生成新的密钥信息时，更新密钥信息，将新的密钥信息作为密钥信息。
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4.发明授权Memory controller, memory control apparatus, memory device, memory information protection system, control method for memory control apparatus, and control method for memory device 有权存储器控制器，存储器控制装置，存储器件，存储器信息保护系统，存储器控制装置的控制方法以及存储器件的控制方法公开(公告)号：US08826042B2
公开(公告)日：2014-09-02
申请号：US13257680
申请日：2010-04-05
CPC分类号： H04L9/0869 , G06F21/79 , G06F21/80 , H04L9/06 , H04L9/0894 , H04L2209/12
摘要： A technique allowing an improvement in the confidentiality of information stored in a memory device. A memory controller includes a key generation part that newly generates key information for use in encryption and decryption of information at every predetermined timing, and a data conversion circuit that encrypts information to be outputted to a memory device based on the information and decrypts encrypted information inputted from the memory device based on the key information. In the data conversion circuit, each time the key generation part generates new key information, key information is updated so as to set the new key information as the key information.
摘要翻译： 一种允许改善存储在存储装置中的信息的机密性的技术。 存储器控制器包括：新产生用于在每个预定定时对信息进行加密和解密的密钥信息的密钥生成部件;以及数据转换电路，其根据该信息对输出到存储器件的信息进行加密，并解密输入的加密信息 从存储设备基于密钥信息。 在数据转换电路中，每当密钥生成部生成新的密钥信息时，更新密钥信息，将新的密钥信息作为密钥信息。
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公开(公告)号：US08375169B2
公开(公告)日：2013-02-12
申请号：US11968427
申请日：2008-01-02
申请人： Takahiko Sugahara , Tetsuo Furuichi
发明人： Takahiko Sugahara , Tetsuo Furuichi
IPC分类号： G06F13/00
CPC分类号： G06F12/122 , G06F12/0246 , G06F12/0866 , G06F13/1631
摘要： An address comparator stores an address of data read out by a host system. Also, a buffer reads out the data from a memory and stores the data. If an address of data which is expected to be newly read out by the host system is included in addresses which have already been stored in the address comparator, the host system 1 newly reads out the data from the buffer, not from the memory. As a result, it is possible to eliminate or lessen the possibility of unintentional rewriting of data which is likely to be caused due to repeated readout of data.
摘要翻译： 地址比较器存储由主机系统读出的数据的地址。 此外，缓冲器从存储器读出数据并存储数据。 如果预先由主机系统新读出的数据的地址被包含在已经存储在地址比较器中的地址中，则主机系统1不是从存储器中读出来自缓冲器的数据。 结果，可以消除或减少由于重复读出数据而可能引起的数据的无意重写的可能性。
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6.发明授权Memory controller for suppressing read disturb when data is repeatedly read out 有权用于当重复读出数据时抑制读取干扰的存储器控制器公开(公告)号：US08725952B2
公开(公告)日：2014-05-13
申请号：US13618921
申请日：2012-09-14
申请人： Takahiko Sugahara , Tetsuo Furuichi
发明人： Takahiko Sugahara , Tetsuo Furuichi
CPC分类号： G06F12/122 , G06F12/0246 , G06F12/0866 , G06F13/1631
摘要： An address comparator stores an address of data read out by a host system. Also, a buffer reads out the data from a memory and stores the data. If an address of data which is expected to be newly read out by the host system is included in addresses which have already been stored in the address comparator, the host system 1 newly reads out the data from the buffer, not from the memory. As a result, it is possible to eliminate or lessen the possibility of unintentional rewriting of data which is likely to be caused due to repeated readout of data.
摘要翻译： 地址比较器存储由主机系统读出的数据的地址。 此外，缓冲器从存储器读出数据并存储数据。 如果预先由主机系统新读出的数据的地址被包含在已经存储在地址比较器中的地址中，则主机系统1不是从存储器中读出来自缓冲器的数据。 结果，可以消除或减少由于重复读出数据而可能引起的数据的无意重写的可能性。
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公开(公告)号：US07877668B2
公开(公告)日：2011-01-25
申请号：US12115098
申请日：2008-05-05
申请人： Takahiko Sugahara
发明人： Takahiko Sugahara
IPC分类号： G11C29/00
CPC分类号： G06F11/1068 , G11C16/0483 , G11C2029/0411
摘要： When a host system outputs a read command to a memory controller, it measures a load count of a memory area on which a read access load is imposed. Then, when the host system judges that the load count of a memory area reaches a predetermined count, it causes the memory controller to perform an error detection on the memory area. Further, when the host system finds that an error occurs in the memory area, it causes the memory controller to perform an error correction on the memory area. This can avoid or reduce unintended rewriting due to repeated readouts.
摘要翻译： 当主机系统向存储器控制器输出读取命令时，它测量在其上施加读取访问负载的存储器区域的负载计数。 然后，当主机系统判断存储区域的负载计数达到预定计数时，使存储器控制器对存储器区域进行错误检测。 此外，当主机系统发现在存储器区域中发生错误时，它使存储器控制器对存储器区域执行错误校正。 这可以避免或减少由于重复读数导致的意外重写。
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公开(公告)号：US08214725B2
公开(公告)日：2012-07-03
申请号：US12170102
申请日：2008-07-09
申请人： Takahiko Sugahara
发明人： Takahiko Sugahara
IPC分类号： H03M13/00
CPC分类号： G06F11/1068 , G11C29/42 , G11C2029/0409 , G11C2029/0411
摘要： The Error Correction Code (ECC) circuit generates the first syndrome of write data, which have not been written to the memory. The Error Detection Code (EDC) circuit generates the second syndrome of verification read data, which have been written to the memory. The EDC circuit detects errors due only to the “read disturb phenomenon” using the second syndrome, the errors occurring in data scanned from the memory. The ECC circuit detects and corrects errors due to the “program disturb phenomenon” and the “read disturb phenomenon” using the first syndrome, the errors occurring in the data in which the errors due only to the “read disturb phenomenon” have been detected. As a result, both the circuit size and the processing time can be reduced.
摘要翻译： 纠错码（ECC）电路产生尚未写入存储器的写入数据的第一个异常。 错误检测码（EDC）电路产生已被写入存储器的第二个验证读取数据的综合征。 EDC电路仅利用第二次校正器的“读取干扰现象”来检测错误，从存储器扫描的数据中发生错误。 ECC电路使用第一个校正子检测并校正由于“程序干扰现象”和“读取干扰现象”引起的错误，在仅检测到“读取干扰现象”的错误的数据中出现错误。 结果，可以减小电路尺寸和处理时间。
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公开(公告)号：US08949690B2
公开(公告)日：2015-02-03
申请号：US13423566
申请日：2012-03-19
申请人： Takahiko Sugahara , Eri Fukushita
发明人： Takahiko Sugahara , Eri Fukushita
CPC分类号： G06F11/1044 , G06F11/10 , G06F11/1048 , G11C29/42 , H03M13/05 , H03M13/1525 , H03M13/3715 , H03M13/3738 , H03M13/617
摘要： An ECC circuit can operate in a plurality of error correction modes with different correcting capabilities for data stored in a memory. The ECC circuit calculates a syndrome with respect to information data in accordance with an error correction mode set by a control part and adds a syndrome of a fixed length in which dummy bits are added to the calculated syndrome, to the information data. When code data is read out, the ECC circuit performs a correction process on the code data by using the syndrome included in the code data.
摘要翻译： ECC电路可以以对存储在存储器中的数据具有不同校正能力的多个纠错模式进行操作。 ECC电路根据由控制部分设置的纠错模式来计算相对于信息数据的综合征，并将其中加上虚拟比特的固定长度的校正子加到所述信息数据上。 当读出代码数据时，ECC电路通过使用包含在代码数据中的校正子来对代码数据进行校正处理。
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