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公开(公告)号：US08823691B2
公开(公告)日：2014-09-02
申请号：US13348673
申请日：2012-01-12
申请人： Takahiro Ochiai , Mitsuru Goto , Hiroyuki Higashijima , Yoshihiro Kotani , Shuuichirou Matsumoto
发明人： Takahiro Ochiai , Mitsuru Goto , Hiroyuki Higashijima , Yoshihiro Kotani , Shuuichirou Matsumoto
IPC分类号： G09G5/00
CPC分类号： G09G3/3648 , G09G3/3614 , G09G3/3677 , G09G2310/0281 , G09G2320/0219
摘要： A display device includes: plural pixel groups each including pixel circuits; plural scanning lines that are each connected to the pixel circuits included in any one of the pixel groups; a clock signal supply circuit that supplies a clock signal including a pulse signal; a shift register circuit that selectively transmits the pulse signal to the scanning lines in a predetermined order; and data signal lines that are connected to the pixel circuits and that supply a data signal to the pixel circuits included in the pixel group to be scanned. The period of the pulse signal supplied to some of the scanning lines is longer than the period of the pulse signal supplied to the other scanning lines, or the data signal is transmitted by the transistors included in the pixel circuits.
摘要翻译： 显示装置包括：多个像素组，每个像素组包括像素电路; 多个扫描线，其各自连接到包括在任何一个像素组中的像素电路; 时钟信号供给电路，其提供包括脉冲信号的时钟信号; 移位寄存器电路，其以预定顺序选择性地将扫描线传送到扫描线; 以及连接到像素电路并且将数据信号提供给要扫描的像素组中包括的像素电路的数据信号线。 提供给一些扫描线的脉冲信号的周期长于提供给其它扫描线的脉冲信号的周期，或者数据信号由包括在像素电路中的晶体管传输。
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公开(公告)号：US09336899B2
公开(公告)日：2016-05-10
申请号：US13334280
申请日：2011-12-22
申请人： Takahiro Ochiai , Mitsuru Goto , Hiroyuki Higashijima , Yoshihiro Kotani , Shuuichirou Matsumoto
发明人： Takahiro Ochiai , Mitsuru Goto , Hiroyuki Higashijima , Yoshihiro Kotani , Shuuichirou Matsumoto
CPC分类号： G11C19/287 , G09G3/3677 , G09G5/003 , G09G2310/0286 , G09G2310/08 , G09G2330/021
摘要： A bidirectional shift register capable of performing a stable shift operation in both directions and an image display device using the same are provided. In forward shift operation, when reference point N1 is at H level, (n+4)-th unit register circuit as a rear stage of the bidirectional shift register outputs pulse G(n+4) in synchronization with clock pulse V (n+4) inputted to (n+4)-th unit register circuit. A backward direction trigger signal VSTB is generated not only at the time of start of backward shift, but also, for example, in period (time t4 to t5) of one-phase clock immediately after G(n+4) is outputted in vertical blanking interval of the forward shift. The backward direction trigger signal VSTB is inputted to gate of a transistor provided to set reference point N1 of (n+4)-th unit register circuit to H level at the time of start of the backward shift.
摘要翻译： 提供能够在两个方向上执行稳定的移位操作的双向移位寄存器和使用其的图像显示装置。 在正向移位操作中，当参考点N1处于H电平时，作为双向移位寄存器的后级的第（n + 4）单位寄存器电路与时钟脉冲V（n + 4）同步地输出脉冲G（n + 4）输入到第（n + 4）个单元寄存器电路。 不仅在反向开始时产生反向触发信号VSTB，而且例如在紧接在G（n + 4）之后的单相时钟的周期（时刻t4〜t5）中垂直输出 向前移位的消隐间隔。 反向触发信号VSTB被输入到在第（n + 4）个单位寄存器电路的参考点N1设置为H电平的晶体管的栅极上，在反向启动时为止。
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公开(公告)号：US20120182279A1
公开(公告)日：2012-07-19
申请号：US13348673
申请日：2012-01-12
申请人： Takahiro OCHIAI , Mitsuru Goto , Hiroyuki Higashijima , Yoshihiro Kotani , Shuuichirou Matsumoto
发明人： Takahiro OCHIAI , Mitsuru Goto , Hiroyuki Higashijima , Yoshihiro Kotani , Shuuichirou Matsumoto
IPC分类号： G09G5/00
CPC分类号： G09G3/3648 , G09G3/3614 , G09G3/3677 , G09G2310/0281 , G09G2320/0219
摘要： A display device includes: plural pixel groups each including pixel circuits; plural scanning lines that are each connected to the pixel circuits included in any one of the pixel groups; a clock signal supply circuit that supplies a clock signal including a pulse signal; a shift register circuit that selectively transmits the pulse signal to the scanning lines in a predetermined order; and data signal lines that are connected to the pixel circuits and that supply a data signal to the pixel circuits included in the pixel group to be scanned. The period of the pulse signal supplied to some of the scanning lines is longer than the period of the pulse signal supplied to the other scanning lines, or the data signal is transmitted by the transistors included in the pixel circuits.
摘要翻译： 显示装置包括：多个像素组，每个像素组包括像素电路; 多个扫描线，其各自连接到包括在任何一个像素组中的像素电路; 时钟信号供给电路，其提供包括脉冲信号的时钟信号; 移位寄存器电路，其以预定顺序选择性地将扫描线传送到扫描线; 以及连接到像素电路并且将数据信号提供给要扫描的像素组中包括的像素电路的数据信号线。 提供给一些扫描线的脉冲信号的周期长于提供给其它扫描线的脉冲信号的周期，或者数据信号由包括在像素电路中的晶体管传输。
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公开(公告)号：US08576214B2
公开(公告)日：2013-11-05
申请号：US12709254
申请日：2010-02-19
CPC分类号： H03F3/345 , G09G2310/027 , G09G2310/0297 , H03F3/45179
摘要： A circuit that obtains a more accurate, output voltage from a plurality of input voltages is provided. A two-input single-output circuit includes a current source transistor allowing a predetermined current to flow, a cascode transistor section including two MOS transistors that are cascode-connected to the drain side of the current source transistor and have the same characteristics, a differential pair section having a first differential pair formed of a first input-side transistor and a first output-side transistor whose source lines are shared and a second differential pair formed of a second input-side transistor and a second output-side transistor whose source lines are shared, and a current mirror circuit section. Drain lines of the transistors of the cascade transistor section are respectively connected to the source lines of the first and second differential pairs.
摘要翻译： 提供从多个输入电压获得更精确的输出电压的电路。 双输入单输出电路包括允许预定电流流动的电流源晶体管，共源共栅晶体管部分，其包括共源共栅式连接到电流源晶体管的漏极侧并具有相同特性的两个MOS晶体管，差分 所述第一差分对具有由第一输入侧晶体管和源极线共享的第一输出侧晶体管和由第二输入侧晶体管和第二输出侧晶体管形成的第二差分对形成的第一差分对， 被共享，并且是电流镜电路部分。 级联晶体管部分的晶体管的漏极线分别连接到第一和第二差分对的源极线。
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公开(公告)号：US20100245320A1
公开(公告)日：2010-09-30
申请号：US12700787
申请日：2010-02-05
IPC分类号： G09G5/00
CPC分类号： G09G3/3688 , G09G2310/027
摘要： An object of the invention is to reduce the size of a decoder circuit of a display device. A decoder circuit which outputs voltages corresponding to 8-bit digital values includes a predecoder section, which includes an A decoder, B decoder, and C decoder, each of which is configured of a matrix type decoder circuit which carries out a three bits' worth of decoding, and a tournament type decoder circuit which carries out a three bits' worth of decoding, a selection circuit which, having input thereinto three voltages output respectively from the A decoder, B decoder, and C decoder, and applied to three output signal lines, selects two voltages of the three input voltages using a bit with one of the digital values and applies them to two output signal lines, and an intermediate voltage output circuit which, having input thereinto the two voltages selected by the selection circuit, outputs a voltage which is the average of the two voltages.
摘要翻译： 本发明的目的是减小显示装置的解码器电路的尺寸。 输出对应于8位数字值的电压的解码器电路包括预解码器部分，其包括A解码器，B解码器和C解码器，每个解码器部分由执行三比特值的矩阵型解码器电路 的解码，以及执行三比特解码的比赛型解码器电路，选择电路，其输入分别从A解码器，B解码器和C解码器输出的三个电压，并且应用于三个输出信号 使用具有数字值之一的位选择三个输入电压的两个电压，并将其施加到两个输出信号线，并且输入其中由选择电路选择的两个电压的中间电压输出电路输出一个 电压是两个电压的平均值。
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公开(公告)号：US20120162287A1
公开(公告)日：2012-06-28
申请号：US13334233
申请日：2011-12-22
IPC分类号： G09G5/10
CPC分类号： G09G3/3688 , G09G3/3614 , G09G3/3655 , G09G3/3696 , G09G2310/027 , G09G2310/0291 , G09G2310/0297 , G09G2320/0219 , G09G2320/0238 , G09G2320/0276 , G09G2330/028
摘要： A driver circuit including a DA converting circuit that converts video data input from the outside to a grayscale voltage; an amplifying circuit that amplifies the grayscale voltage; and a switch circuit that selects the grayscale voltage output from the amplifying circuit and a predetermined voltage as a voltage that is output to the image line. When video data indicating a minimum grayscale, the switch circuit outputs the predetermined voltage to the image line, and when video data indicating a grayscale other than the minimum grayscale is input, the switch circuit outputs the grayscale voltage output from the amplifying circuit to the image line. The predetermined voltage allows a voltage of the pixel electrode and a voltage of the counter electrode after passage of the writing of the image voltage to be coincident with each other.
摘要翻译： 一种驱动电路，包括将从外部输入的视频数据转换为灰度电压的DA转换电路; 放大电路，放大灰度电压; 以及开关电路，其选择从放大电路输出的灰度电压和预定电压作为输出到图像线的电压。 当指示最小灰度的视频数据时，开关电路将预定电压输出到图像行，并且当输入指示除最小灰度之外的灰度的视频数据时，开关电路将从放大电路输出的灰度电压输出到图像 线。 预定电压允许像素电极的电压和对准电极的电压在写入图像电压之后彼此一致。
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公开(公告)号：US20100238153A1
公开(公告)日：2010-09-23
申请号：US12709254
申请日：2010-02-19
IPC分类号： G06F3/038
CPC分类号： H03F3/345 , G09G2310/027 , G09G2310/0297 , H03F3/45179
摘要： A circuit that obtains a more accurate, output voltage from a plurality of input voltages is provided. A two-input single-output circuit includes a current source transistor allowing a predetermined current to flow, a cascode transistor section including two MOS transistors that are cascode-connected to the drain side of the current source transistor and have the same characteristics, a differential pair section having a first differential pair formed of a first input-side transistor and a first output-side transistor whose source lines are shared and a second differential pair formed of a second input-side transistor and a second output-side transistor whose source lines are shared, and a current mirror circuit section. Drain lines of the transistors of the cascade transistor section are respectively connected to the source lines of the first and second differential pairs.
摘要翻译： 提供从多个输入电压获得更精确的输出电压的电路。 双输入单输出电路包括允许预定电流流动的电流源晶体管，共源共栅晶体管部分，其包括共源共栅式连接到电流源晶体管的漏极侧并具有相同特性的两个MOS晶体管，差分 所述第一差分对具有由第一输入侧晶体管和源极线共享的第一输出侧晶体管和由第二输入侧晶体管和第二输出侧晶体管形成的第二差分对形成的第一差分对， 被共享，并且是电流镜电路部分。 级联晶体管部分的晶体管的漏极线分别连接到第一和第二差分对的源极线。
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公开(公告)号：US08610698B2
公开(公告)日：2013-12-17
申请号：US12700755
申请日：2010-02-05
申请人： Taku Saito , Shuuichirou Matsumoto , Mitsuru Goto
发明人： Taku Saito , Shuuichirou Matsumoto , Mitsuru Goto
CPC分类号： G09G3/2007 , G09G3/3696 , G09G2300/0426 , G09G2300/0439 , G09G2320/0247 , G09G2330/028
摘要： To provide a display device including a switching regulator type power generating circuit which realizes an increase in display quality by an output voltage being more stable, and by suppressing a flickering of a screen. A display device includes a switching regulator type direct current power generating circuit, wherein a period for which a switching element is turned on is determined in such a way as to increase or decrease by a given width when a code of an output voltage with respect to a setting voltage is constant, and the period is determined in such a way as to increase or decrease differently from the given width when the code changes.
摘要翻译： 提供一种包括开关调节器型发电电路的显示装置，其通过更稳定的输出电压实现显示质量的提高，并且通过抑制屏幕的闪烁。 显示装置包括开关调节器型直流发电电路，其中开关元件导通的周期以当相对于输出电压的输出电压的代码相对于增加或减小给定宽度的方式被确定时 设定电压是恒定的，并且当代码改变时，以与给定宽度不同的方式增加或减少该周期。
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9.发明授权Driver circuit for image lines of a display device with arrangement to improve multi-level grayscale display 有权用于显示装置的图像线路的驱动电路，具有改善多级灰阶显示的布置公开(公告)号：US09165523B2
公开(公告)日：2015-10-20
申请号：US13334233
申请日：2011-12-22
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G3/3614 , G09G3/3655 , G09G3/3696 , G09G2310/027 , G09G2310/0291 , G09G2310/0297 , G09G2320/0219 , G09G2320/0238 , G09G2320/0276 , G09G2330/028
摘要： A driver circuit including a DA converting circuit that converts video data input from the outside to a grayscale voltage; an amplifying circuit that amplifies the grayscale voltage; and a switch circuit that selects the grayscale voltage output from the amplifying circuit and a predetermined voltage as a voltage that is output to the image line. When video data indicating a minimum grayscale, the switch circuit outputs the predetermined voltage to the image line, and when video data indicating a grayscale other than the minimum grayscale is input, the switch circuit outputs the grayscale voltage output from the amplifying circuit to the image line. The predetermined voltage allows a voltage of the pixel electrode and a voltage of the counter electrode after passage of the writing of the image voltage to be coincident with each other.
摘要翻译： 一种驱动电路，包括将从外部输入的视频数据转换为灰度电压的DA转换电路; 放大电路，放大灰度电压; 以及开关电路，其选择从放大电路输出的灰度电压和预定电压作为输出到图像线的电压。 当指示最小灰度的视频数据时，开关电路将预定电压输出到图像行，并且当输入指示除最小灰度之外的灰度的视频数据时，开关电路将从放大电路输出的灰度电压输出到图像 线。 预定电压允许像素电极的电压和对准电极的电压在写入图像电压之后彼此一致。
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公开(公告)号：US08610699B2
公开(公告)日：2013-12-17
申请号：US12700787
申请日：2010-02-05
IPC分类号： G09G5/00
CPC分类号： G09G3/3688 , G09G2310/027
摘要： An object of the invention is to reduce the size of a decoder circuit of a display device. A decoder circuit which outputs voltages corresponding to 8-bit digital values includes a predecoder section, which includes an A decoder, B decoder, and C decoder, each of which is configured of a matrix type decoder circuit which carries out a three bits' worth of decoding, and a tournament type decoder circuit which carries out a three bits' worth of decoding, a selection circuit which, having input thereinto three voltages output respectively from the A decoder, B decoder, and C decoder, and applied to three output signal lines, selects two voltages of the three input voltages using a bit with one of the digital values and applies them to two output signal lines, and an intermediate voltage output circuit which, having input thereinto the two voltages selected by the selection circuit, outputs a voltage which is the average of the two voltages.
摘要翻译： 本发明的目的是减小显示装置的解码器电路的尺寸。 输出对应于8位数字值的电压的解码器电路包括预解码器部分，其包括A解码器，B解码器和C解码器，每个解码器部分由执行三比特值的矩阵型解码器电路 的解码，以及执行三比特解码的比赛型解码器电路，选择电路，其输入分别从A解码器，B解码器和C解码器输出的三个电压，并且应用于三个输出信号 使用具有数字值之一的位选择三个输入电压的两个电压，并将其施加到两个输出信号线，并且输入其中由选择电路选择的两个电压的中间电压输出电路输出一个 电压是两个电压的平均值。
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