公开(公告)号：US09035864B2

公开(公告)日：2015-05-19

申请号：US12831352

申请日：2010-07-07

申请人： Takahiro Ochiai ,  Mitsuru Goto ,  Youzou Nakayasu ,  Yuki Okada ,  Naoki Takada

发明人： Takahiro Ochiai ,  Mitsuru Goto ,  Youzou Nakayasu ,  Yuki Okada ,  Naoki Takada

IPC分类号： G09G3/36 ,  G11C19/28

CPC分类号： G09G3/3677 ,  G09G2320/043 ,  G11C19/28

摘要： A gate signal line drive circuit and a display device which realize the suppression of a threshold voltage of an element which is used for a long time are provided. With respect to elements to which a HIGH voltage is applied for a long time, a plurality of elements are connected parallel to each other and are controlled such that at least any one of the plurality of elements is driven by a switching element, and a period during which the element is not driven is set longer than a frame display period.

摘要翻译： 提供了一种实现对长时间使用的元件的阈值电压的抑制的栅极信号线驱动电路和显示装置。 对于长时间施加高电压的元件，多个元件彼此并联连接并被控制为使得多个元件中的至少任一个被开关元件驱动，并且周期 元件未被驱动的时间长于帧显示周期。

公开(公告)号：US20100328281A1

公开(公告)日：2010-12-30

申请号：US12822661

申请日：2010-06-24

申请人： Yuki OKADA ,  Mitsuru Goto ,  Takahiro Ochiai ,  Naoki Takada ,  Youzou Nakayasu

发明人： Yuki OKADA ,  Mitsuru Goto ,  Takahiro Ochiai ,  Naoki Takada ,  Youzou Nakayasu

IPC分类号： G06F3/038

CPC分类号： G11C19/28 ,  G09G3/3266 ,  G09G2310/0286 ,  G11C19/184

摘要： Each shift register includes a first element controlled by a first potential node to supply a first driving voltage to an output terminal, a second element controlled by a second potential node to supply a second driving voltage lower than the first driving voltage to the output terminal, and a third element for controlling the first potential node and the second potential node so as to have opposite potential levels. Voltages are applied to the third element so that a state of A>B and A>C and a state of A B and A C, or a state of A C and a state of A>B and A

摘要翻译： 每个移位寄存器包括由第一电势节点控制以向输出端提供第一驱动电压的第一元件，由第二电势节点控制的第二元件，以将低于第一驱动电压的第二驱动电压提供给输出端， 以及用于控制第一电位节点和第二电位节点以便具有相反电位电平的第三元件。 电压施加到第三元件，使得A> B和A> C的状态和A B和A C或A C的状态和A> B和A

公开(公告)号：US20100302217A1

公开(公告)日：2010-12-02

申请号：US12785800

申请日：2010-05-24

申请人： Takahiro OCHIAI ,  Mitsuru Goto ,  Youzou Nakayasu ,  Yuki Okada ,  Naoki Takada

发明人： Takahiro OCHIAI ,  Mitsuru Goto ,  Youzou Nakayasu ,  Yuki Okada ,  Naoki Takada

IPC分类号： G06F3/038 ,  H03K3/00

CPC分类号： G09G3/3696 ,  G09G3/3674 ,  G09G2300/0434

摘要： A gate signal line driving circuit which suppresses noises in a gate signal and a display device which uses the gate signal line driving circuit are provided. A first basic circuit provided to a gate signal line driving circuit includes a HIGH voltage applying switching element which applies a HIGH voltage to gate signal lines in response to a signal HIGH period, and a LOW voltage applying switching circuit which applies a LOW voltage to the gate signal lines in response to a signal LOW period. In response to a signal HIGH period, a switch of the LOW voltage applying switching circuit of the first basic circuit is turned off based on a signal applied to a switch of the HIGH voltage applying switching element of a second basic circuit which assumes a signal HIGH period earlier than the first basic circuit.

摘要翻译： 提供了抑制门信号中的噪声的门信号线驱动电路和使用栅信号线驱动电路的显示装置。 提供给栅极信号线驱动电路的第一基本电路包括：高电压施加开关元件，其响应于信号高电平周期向栅极信号线施加HIGH电压;以及低电压施加开关电路，其向所述低电压施加开关元件施加低电压 门信号线响应于信号低电平周期。 响应于信号高电平周期，第一基本电路的低电压施加开关电路的开关基于施加到假设信号为高的第二基本电路的高电压施加开关元件的开关的信号而截止 比第一个基本电路早。

公开(公告)号：US08854291B2

公开(公告)日：2014-10-07

申请号：US12785800

申请日：2010-05-24

申请人： Takahiro Ochiai ,  Mitsuru Goto ,  Youzou Nakayasu ,  Yuki Okada ,  Naoki Takada

发明人： Takahiro Ochiai ,  Mitsuru Goto ,  Youzou Nakayasu ,  Yuki Okada ,  Naoki Takada

IPC分类号： G09G3/36

CPC分类号： G09G3/3696 ,  G09G3/3674 ,  G09G2300/0434

摘要： A gate signal line driving circuit which suppresses noises in a gate signal and a display device which uses the gate signal line driving circuit are provided. A first basic circuit provided to a gate signal line driving circuit includes a HIGH voltage applying switching element which applies a HIGH voltage to gate signal lines in response to a signal HIGH period, and a LOW voltage applying switching circuit which applies a LOW voltage to the gate signal lines in response to a signal LOW period. In response to a signal HIGH period, a switch of the LOW voltage applying switching circuit of the first basic circuit is turned off based on a signal applied to a switch of the HIGH voltage applying switching element of a second basic circuit which assumes a signal HIGH period earlier than the first basic circuit.

摘要翻译： 提供了抑制门信号中的噪声的门信号线驱动电路和使用栅信号线驱动电路的显示装置。 提供给栅极信号线驱动电路的第一基本电路包括：高电压施加开关元件，其响应于信号高电平周期向栅极信号线施加HIGH电压;以及低电压施加开关电路，其向所述低电压施加开关元件施加低电压 门信号线响应于信号低电平周期。 响应于信号高电平周期，第一基本电路的低电压施加开关电路的开关基于施加到假设信号为高的第二基本电路的高电压施加开关元件的开关的信号而截止 比第一个基本电路早。

公开(公告)号：US08451260B2

公开(公告)日：2013-05-28

申请号：US12822661

申请日：2010-06-24

申请人： Yuki Okada ,  Mitsuru Goto ,  Takahiro Ochiai ,  Naoki Takada ,  Youzou Nakayasu

发明人： Yuki Okada ,  Mitsuru Goto ,  Takahiro Ochiai ,  Naoki Takada ,  Youzou Nakayasu

IPC分类号： G06F3/038

CPC分类号： G11C19/28 ,  G09G3/3266 ,  G09G2310/0286 ,  G11C19/184

摘要： Each shift register includes a first element controlled by a first potential node to supply a first driving voltage to an output terminal, a second element controlled by a second potential node to supply a second driving voltage lower than the first driving voltage to the output terminal, and a third element for controlling the first potential node and the second potential node so as to have opposite potential levels. Voltages are applied to the third element so that a state of A>B and A>C and a state of A B and A C, or a state of A C and a state of A>B and A

摘要翻译： 每个移位寄存器包括由第一电势节点控制以向输出端提供第一驱动电压的第一元件，由第二电势节点控制的第二元件，以将低于第一驱动电压的第二驱动电压提供给输出端， 以及用于控制第一电位节点和第二电位节点以便具有相反电位电平的第三元件。 电压施加到第三元件，使得A> B和A> C的状态和A B和A C或A C的状态和A> B和A

公开(公告)号：US20110007061A1

公开(公告)日：2011-01-13

申请号：US12831352

申请日：2010-07-07

申请人： Takahiro OCHIAI ,  Mitsuru Goto ,  Youzou Nakayasu ,  Yuki Okada ,  Naoki Takada

发明人： Takahiro OCHIAI ,  Mitsuru Goto ,  Youzou Nakayasu ,  Yuki Okada ,  Naoki Takada

IPC分类号： G09G5/00 ,  G09G3/36

CPC分类号： G09G3/3677 ,  G09G2320/043 ,  G11C19/28

摘要： A gate signal line drive circuit and a display device which realize the suppression of a threshold voltage of an element which is used for a long time are provided. With respect to elements to which a HIGH voltage is applied for a long time, a plurality of elements are connected parallel to each other and are controlled such that at least any one of the plurality of elements is driven by a switching element, and a period during which the element is not driven is set longer than a frame display period.

摘要翻译： 提供了一种实现对长时间使用的元件的阈值电压的抑制的栅极信号线驱动电路和显示装置。 对于长时间施加高电压的元件，多个元件彼此并联连接并被控制为使得多个元件中的至少任一个被开关元件驱动，并且周期 元件未被驱动的时间长于帧显示周期。

公开(公告)号：US08339390B2

公开(公告)日：2012-12-25

申请号：US12625683

申请日：2009-11-25

申请人： Naoki Takada ,  Naruhiko Kasai ,  Takuya Eriguchi ,  Yuki Okada ,  Mitsuru Goto ,  Yoshihiro Kotani

发明人： Naoki Takada ,  Naruhiko Kasai ,  Takuya Eriguchi ,  Yuki Okada ,  Mitsuru Goto ,  Yoshihiro Kotani

IPC分类号： G06F3/038

CPC分类号： G09G3/3696 ,  G09G2330/02 ,  G09G2330/021 ,  H02M3/07 ,  H02M3/156 ,  H02M2001/0032 ,  Y02B70/16

摘要： Provided are a power supply circuit and a display device which are capable of enhancing power efficiency even when applied to a display panel whose current consumption varies. The power supply circuit boosts and outputs an input voltage using a booster chopper circuit. A frequency control circuit changes a frequency of a clock signal, which controls a switch of the chopper circuit, in accordance with a load of the power supply circuit. The frequency control circuit divides an operation of the display device into a display effective period at a high load and a vertical retrace period at a low load, based on a vertical synchronizing signal and a horizontal synchronizing signal. The frequency control circuit sets the frequency of the clock signal in a high-load period to be higher than that in a low-load period.

摘要翻译： 提供了即使在电流消耗变化的显示面板上也能够提高功率效率的电源电路和显示装置。 电源电路使用升压斩波电路来提升输出电压。 频率控制电路根据电源电路的负载改变控制斩波电路的开关的时钟信号的频率。 频率控制电路基于垂直同步信号和水平同步信号，在低负载下将显示装置的操作划分为高负载和垂直回扫周期的显示有效期间。 频率控制电路将高负载时段的时钟信号的频率设定为比低负载期间的频率高。

公开(公告)号：US20100128022A1

公开(公告)日：2010-05-27

申请号：US12625683

申请日：2009-11-25

申请人： Naoki Takada ,  Naruhiko Kasai ,  Takuya Eriguchi ,  Yuki Okada ,  Mitsuru Goto ,  Yoshihiro Kotani

发明人： Naoki Takada ,  Naruhiko Kasai ,  Takuya Eriguchi ,  Yuki Okada ,  Mitsuru Goto ,  Yoshihiro Kotani

IPC分类号： G06F3/038

CPC分类号： G09G3/3696 ,  G09G2330/02 ,  G09G2330/021 ,  H02M3/07 ,  H02M3/156 ,  H02M2001/0032 ,  Y02B70/16

摘要： Provided are a power supply circuit and a display device which are capable of enhancing power efficiency even when applied to a display panel whose current consumption varies. The power supply circuit boosts and outputs an input voltage using a booster chopper circuit. A frequency control circuit changes a frequency of a clock signal, which controls a switch of the chopper circuit, in accordance with a load of the power supply circuit. The frequency control circuit divides an operation of the display device into a display effective period at a high load and a vertical retrace period at a low load, based on a vertical synchronizing signal and a horizontal synchronizing signal. The frequency control circuit sets the frequency of the clock signal in a high-load period to be higher than that in a low-load period.

摘要翻译： 提供了即使在电流消耗变化的显示面板上也能够提高功率效率的电源电路和显示装置。 电源电路使用升压斩波电路来提升输出电压。 频率控制电路根据电源电路的负载改变控制斩波电路的开关的时钟信号的频率。 频率控制电路基于垂直同步信号和水平同步信号，在低负载下将显示装置的操作划分为高负载和垂直回扫周期的显示有效期间。 频率控制电路将高负载时段的时钟信号的频率设定为比低负载期间的频率高。

公开(公告)号：US08674973B2

公开(公告)日：2014-03-18

申请号：US12844877

申请日：2010-07-28

申请人： Naoki Takada ,  Naruhiko Kasai ,  Norio Mamba ,  Mitsuru Goto ,  Shuuichirou Matsumoto

发明人： Naoki Takada ,  Naruhiko Kasai ,  Norio Mamba ,  Mitsuru Goto ,  Shuuichirou Matsumoto

IPC分类号： G09G5/00 ,  G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/3614 ,  G09G2310/0248 ,  G09G2310/0297 ,  G09G2320/0247 ,  G09G2330/021

摘要： A liquid crystal display device employing a dot inversion drive method includes a pixel array, a data driver circuit, a short circuit, and a scanning circuit. The short circuit is disposed for respective outputs of the data driver circuit, and includes a switching element for connecting each of the outputs to a precharge voltage different from an output voltage. The short circuit includes the switching element disposed in one of a first switching group and a second switching group; the switching element of one of the first switching group and the second switching group is connected to respective pairs of pixel column units including an odd-numbered pixel column and an even-numbered pixel column which are adjacent to each other; and the pairs of pixel column units which are adjacent to each other are each connected to the switching element disposed in respective switching groups different from each other.

摘要翻译： 采用点反转驱动方法的液晶显示装置包括像素阵列，数据驱动电路，短路和扫描电路。 为数据驱动电路的各个输出设置短路，并且包括用于将每个输出连接到不同于输出电压的预充电电压的开关元件。 短路包括设置在第一开关组和第二开关组之一中的开关元件; 第一开关组和第二开关组之一的开关元件连接到彼此相邻的包括奇数像素列和偶数像素列的各对像素列单元; 并且彼此相邻的像素列单元对各自连接到彼此不同的设置在各个开关组中的开关元件。

公开(公告)号：US09961295B2

公开(公告)日：2018-05-01

申请号：US14407045

申请日：2012-06-22

申请人： Naoki Takada

发明人： Naoki Takada

IPC分类号： H04N5/775 ,  H04N9/80 ,  G06F3/14 ,  H04N5/765 ,  H04N9/87 ,  H04N21/41 ,  H04N21/414 ,  H04N21/432 ,  H04N21/4402 ,  H04N21/81 ,  G06Q30/02 ,  G11B27/34 ,  H04N9/30 ,  G09G3/34 ,  H04N5/64

CPC分类号： H04N5/775 ,  G06F3/1446 ,  G06Q30/0272 ,  G09G3/3406 ,  G09G2300/026 ,  G09G2340/045 ,  G11B27/34 ,  H04N5/64 ,  H04N5/765 ,  H04N9/30 ,  H04N9/87 ,  H04N21/4122 ,  H04N21/41415 ,  H04N21/4325 ,  H04N21/440263 ,  H04N21/812

摘要： A display device includes: a display panel that displays an input video signal; and a video recording and reproduction unit that records and reproduces a video picture to be displayed on the display panel. The video recording and reproduction unit includes an image-size setting unit that reduces a size of a screen of the input video signal according to a multi-display configuration.