公开(公告)号：US08354706B2

公开(公告)日：2013-01-15

申请号：US12719193

申请日：2010-03-08

申请人： Takahisa Kanemura ,  Tomomi Kusaka ,  Takashi Izumida ,  Masaki Kondo ,  Nobutoshi Aoki

发明人： Takahisa Kanemura ,  Tomomi Kusaka ,  Takashi Izumida ,  Masaki Kondo ,  Nobutoshi Aoki

IPC分类号： H01L29/788

CPC分类号： H01L29/7883 ,  G11C16/0441 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324

摘要： A semiconductor memory device according to an embodiment of the present invention includes a substrate, a first gate insulator formed on the substrate and serving as an F-N (Fowler-Nordheim) tunneling film, a first floating gate formed on the first gate insulator, a second gate insulator formed on the first floating gate and serving as an F-N tunneling film, a second floating gate formed on the second gate insulator, an intergate insulator formed on the second floating gate and serving as a charge blocking film, and a control gate formed on the intergate insulator, at least one of the first and second floating gates including a metal layer.

摘要翻译： 根据本发明实施例的半导体存储器件包括衬底，形成在衬底上并用作FN（Fowler-Nordheim）隧穿膜的第一栅极绝缘体，形成在第一栅绝缘体上的第一浮栅，第二栅绝缘体 形成在第一浮栅上并用作FN隧穿膜的栅极绝缘体，形成在第二栅极绝缘体上的第二浮栅，形成在第二浮栅上并用作电荷阻挡膜的栅极绝缘体，以及形成在栅极绝缘体上的控制栅极 所述隔间绝缘体，所述第一和第二浮动栅极中的至少一个包括金属层。

公开(公告)号：US20110231174A1

公开(公告)日：2011-09-22

申请号：US13116317

申请日：2011-05-26

申请人： Tomomi Kusaka ,  Takahisa Kanemura

发明人： Tomomi Kusaka ,  Takahisa Kanemura

IPC分类号： G06G7/62

CPC分类号： H01L21/2236 ,  H01J37/32412

摘要： A process simulation method includes: converting condition data of plasma doping for introducing an impurity into a semiconductor in a plasma atmosphere to corresponding condition data of ion implantation for implanting impurities as an ion beam into the semiconductor; and calculating device structure data on the basis of the ion implantation condition data converted from the plasma doping condition data.

摘要翻译： 一种过程模拟方法包括：将等离子体掺杂的条件数据转换成等离子体气氛中的半导体中的等离子体掺杂物，作为离子注入的对应条件数据，将作为离子束的杂质注入到半导体中; 以及基于从等离子体掺杂条件数据转换的离子注入条件数据来计算器件结构数据。

公开(公告)号：US08148217B2

公开(公告)日：2012-04-03

申请号：US13099587

申请日：2011-05-03

申请人： Takashi Izumida ,  Sanae Ito ,  Takahisa Kanemura

发明人： Takashi Izumida ,  Sanae Ito ,  Takahisa Kanemura

IPC分类号： H01L21/00

CPC分类号： H01L29/785 ,  H01L29/66818 ,  H01L29/78609

摘要： A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the projecting semiconductor layer, doping a first-conductivity-type impurity into the first insulating layer, thereby forming a high-impurity-concentration layer in the lower portion of the projecting semiconductor layer, forming gate insulating films on side surfaces of the projecting semiconductor layer which upwardly extend from an upper surface of the first insulating layer, and forming a gate electrode on the gate insulating films and on the first insulating film.

摘要翻译： 制造半导体器件的方法包括在第一导电型半导体衬底上形成掩模层，使用掩模层作为掩模蚀刻半导体衬底，从而形成突出半导体层，在半导体衬底上形成第一绝缘层 为了覆盖突出半导体层的下部，将第一导电型杂质掺杂到第一绝缘层中，从而在突出半导体层的下部形成高杂质浓度层，在侧面形成栅极绝缘膜 所述突出半导体层的表面从所述第一绝缘层的上表面向上延伸，并且在所述栅极绝缘膜上和所述第一绝缘膜上形成栅电极。

公开(公告)号：US20110207309A1

公开(公告)日：2011-08-25

申请号：US13099587

申请日：2011-05-03

申请人： Takashi IZUMIDA ,  Sanae Ito ,  Takahisa Kanemura

发明人： Takashi IZUMIDA ,  Sanae Ito ,  Takahisa Kanemura

IPC分类号： H01L21/28

CPC分类号： H01L29/785 ,  H01L29/66818 ,  H01L29/78609

摘要： A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the projecting semiconductor layer, doping a first-conductivity-type impurity into the first insulating layer, thereby forming a high-impurity-concentration layer in the lower portion of the projecting semiconductor layer, forming gate insulating films on side surfaces of the projecting semiconductor layer which upwardly extend from an upper surface of the first insulating layer, and forming a gate electrode on the gate insulating films and on the first insulating film.

摘要翻译： 制造半导体器件的方法包括在第一导电型半导体衬底上形成掩模层，使用掩模层作为掩模蚀刻半导体衬底，从而形成突出半导体层，在半导体衬底上形成第一绝缘层 为了覆盖突出半导体层的下部，将第一导电型杂质掺杂到第一绝缘层中，从而在突出半导体层的下部形成高杂质浓度层，在侧面形成栅极绝缘膜 所述突出半导体层的表面从所述第一绝缘层的上表面向上延伸，并且在所述栅极绝缘膜上和所述第一绝缘膜上形成栅电极。

公开(公告)号：US07842998B2

公开(公告)日：2010-11-30

申请号：US12248449

申请日：2008-10-09

申请人： Takahisa Kanemura ,  Takashi Izumida ,  Nobutoshi Aoki

发明人： Takahisa Kanemura ,  Takashi Izumida ,  Nobutoshi Aoki

IPC分类号： H01L29/792

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory device including: a semiconductor substrate; memory cell transistors that are series-connected; and a select transistor that includes: a first diffusion region that is formed in the semiconductor substrate at one end of the memory cell transistors; a first insulating film that is formed on the semiconductor substrate at a side of the first diffusion region; a select gate electrode that is formed on the first insulating film; a semiconductor pillar that is formed to extend upward from the semiconductor substrate and to be separated from the select gate electrode; a second insulating film that is formed between the select gate electrode and the semiconductor pillar; and a second diffusion region that is formed on the semiconductor pillar.

摘要翻译： 根据本发明的一个方面，提供了一种非易失性半导体存储器件，包括：半导体衬底; 串联连接的存储单元晶体管; 以及选择晶体管，其包括：在所述存储单元晶体管的一端形成在所述半导体衬底中的第一扩散区域; 在所述第一扩散区域的一侧形成在所述半导体基板上的第一绝缘膜; 形成在所述第一绝缘膜上的选择栅电极; 形成为从半导体衬底向上延伸并与选择栅电极分离的半导体柱; 形成在选择栅电极和半导体柱之间的第二绝缘膜; 以及形成在所述半导体柱上的第二扩散区域。

公开(公告)号：US07662679B2

公开(公告)日：2010-02-16

申请号：US11203425

申请日：2005-08-15

申请人： Takashi Izumida ,  Sanae Ito ,  Takahisa Kanemura

发明人： Takashi Izumida ,  Sanae Ito ,  Takahisa Kanemura

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66818 ,  H01L29/78609

摘要： A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the projecting semiconductor layer, doping a first-conductivity-type impurity into the first insulating layer, thereby forming a high-impurity-concentration layer in the lower portion of the projecting semiconductor layer, forming gate insulating films on side surfaces of the projecting semiconductor layer which upwardly extend from an upper surface of the first insulating layer, and forming a gate electrode on the gate insulating films and on the first insulating film.

摘要翻译： 制造半导体器件的方法包括在第一导电型半导体衬底上形成掩模层，使用掩模层作为掩模蚀刻半导体衬底，从而形成突出半导体层，在半导体衬底上形成第一绝缘层 为了覆盖突出半导体层的下部，将第一导电型杂质掺杂到第一绝缘层中，从而在突出半导体层的下部形成高杂质浓度层，在侧面形成栅极绝缘膜 所述突出半导体层的表面从所述第一绝缘层的上表面向上延伸，并且在所述栅极绝缘膜上和所述第一绝缘膜上形成栅电极。

公开(公告)号：US20100295112A1

公开(公告)日：2010-11-25

申请号：US12721757

申请日：2010-03-11

申请人： Takashi Izumida ,  Nobutoshi Aoki ,  Masaki Kondo ,  Takahisa Kanemura

发明人： Takashi Izumida ,  Nobutoshi Aoki ,  Masaki Kondo ,  Takahisa Kanemura

IPC分类号： H01L27/115

CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7883

摘要： A semiconductor storage device has a semiconductor substrate, a plurality of first insulating films formed on the semiconductor substrate with predetermined spacing therebetween, an element isolation region formed between the first insulating films in a first direction, a floating gate electrode comprising a first charge accumulation film formed on the first insulating film, a second charge accumulation film formed on the first charge accumulation film and having a width in a second direction orthogonal to the first direction smaller than the width of the first charge accumulation film, and a third charge accumulation film formed on the second charge accumulation film and having the width in the second direction larger than the width of the second charge accumulation film, a second insulating film formed on the second charge accumulation film and between the second charge accumulation film and the element isolation region, a third insulating film formed on the charge accumulation film and the element isolation region along the second direction, and a control gate electrode formed on the third insulating film.

摘要翻译： 半导体存储装置具有半导体基板，在半导体基板上形成有规定间隔的多个第一绝缘膜，在第一方向上形成在第一绝缘膜之间的元件隔离区域，包括第一电荷累积膜的浮栅电极 形成在所述第一绝缘膜上的第二电荷累积膜，形成在所述第一电荷累积膜上并且具有与所述第一方向正交的第二方向的宽度小于所述第一电荷累积膜的宽度的第二电荷累积膜，以及形成的第三电荷累积膜 在第二电荷累积膜上并且具有大于第二电荷累积膜的宽度的第二方向的宽度，形成在第二电荷累积膜上以及在第二电荷累积膜和元件隔离区之间的第二绝缘膜， 形成在电荷累积膜上的第三绝缘膜 和沿着第二方向的元件隔离区域，以及形成在第三绝缘膜上的控制栅极电极。

公开(公告)号：US20100178757A1

公开(公告)日：2010-07-15

申请号：US12614912

申请日：2009-11-09

申请人： Tomomi Kusaka ,  Takahisa Kanemura

发明人： Tomomi Kusaka ,  Takahisa Kanemura

IPC分类号： H01L21/265 ,  G06F19/00

CPC分类号： H01L21/2236 ,  H01J37/32412

摘要： A process simulation method includes: converting condition data of plasma doping for introducing an impurity into a semiconductor in a plasma atmosphere to corresponding condition data of ion implantation for implanting impurities as an ion beam into the semiconductor; and calculating device structure data on the basis of the ion implantation condition data converted from the plasma doping condition data.

摘要翻译： 一种过程模拟方法包括：将等离子体掺杂的条件数据转换成等离子体气氛中的半导体中的等离子体掺杂物，作为离子注入的对应条件数据，将作为离子束的杂质注入到半导体中; 以及基于从等离子体掺杂条件数据转换的离子注入条件数据来计算器件结构数据。

公开(公告)号：US20070075342A1

公开(公告)日：2007-04-05

申请号：US11527706

申请日：2006-09-27

申请人： Takahisa Kanemura

发明人： Takahisa Kanemura

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/78618

摘要： A semiconductor device with a fin structure according to one embodiment of the present invention includes: a fin of a predetermined height formed on an insulating layer of a substrate; a gate electrode formed on both sides of the fin through a gate insulating film; and a source/drain region formed in the fin on both sides of the gate electrode by implanting impurities into the fin; wherein a concentration of the impurities forming the source/drain region in a vicinity of an interface between the fin and the insulating layer in the fin is lower than a concentration of the impurities in a vicinity of the interface between the fin and the insulating layer in the insulating layer.

摘要翻译： 根据本发明的一个实施例的具有翅片结构的半导体器件包括：形成在衬底的绝缘层上的预定高度的翅片; 栅极电极，其通过栅极绝缘膜形成在所述鳍片的两侧; 以及通过将杂质注入到所述鳍中而在所述栅电极的两侧的所述翅片中形成的源极/漏极区域; 其特征在于，在所述散热片和所述绝缘层之间的界面附近形成所述源极/漏极区域的所述杂质的浓度低于所述翅片与所述绝缘层之间的界面附近的杂质浓度， 绝缘层。

公开(公告)号：US07197437B2

公开(公告)日：2007-03-27

申请号：US09950278

申请日：2001-09-12

申请人： Takahisa Kanemura

发明人： Takahisa Kanemura

IPC分类号： G06G17/50 ,  G06G7/48 ,  G06F17/50 ,  H01L21/311

CPC分类号： G06F17/5018 ,  G06F2217/06

摘要： A Monte Carlo ion implantation simulation method includes finding a unit cell in which an implanted trial particle is present, finding a basic cell in which the trial particle is present among basic cells that form the unit cell, finding a directional range in which the trial particle travels, obtaining collision candidate atoms with their locations from a database according to the found basic cell and directional range, setting a thermal vibration displacement for each of the collision candidate atoms that has not set thermal vibration displacement, calculating a collision parameter and free-flight distance for each of the collision candidate atoms, selecting, as a collision atom, one of the collision candidate atoms that has a collision parameter smaller than a predetermined maximum collision parameter and a smallest positive free-flight distance, and calculating a collision between the trial particle and the collision atom to find the after-collision location and momentum of the trial particle.

摘要翻译： 蒙特卡罗离子注入模拟方法包括找到其中存在植入的试验颗粒的单元电池，找到其中存在试验颗粒存在于形成单位电池的基本电池中的基本电池，找到试验颗粒的方向范围 根据找到的基本单元和方向范围，从数据库中获取碰撞候选原子及其位置，为未设置热振动位移的每个碰撞候选原子设定热振动位移，计算碰撞参数和自由飞行 每个碰撞候选原子的距离，选择具有小于预定最大碰撞参数和最小正自由飞行距离的碰撞参数的碰撞候选原子之一作为碰撞原子，并计算试验之间的碰撞 颗粒和碰撞原子找到碰撞后的位置和动量 粒子。