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公开(公告)号：US08987829B2
公开(公告)日：2015-03-24
申请号：US12100621
申请日：2008-04-10
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/78
CPC分类号： H01L21/823807 , H01L27/092 , H01L29/7843 , H01L29/7846
摘要： A semiconductor device may include a p-channel semiconductor active region and an n-channel semiconductor active region. An element isolation insulating layer electrically isolates the p-channel semiconductor active region from the n-channel semiconductor active region. An insulating layer made of a different material, being in contact with both ends, in its channel length direction, of the p-channel semiconductor active region applies a compression stress in the channel length direction to a channel of the p-channel semiconductor active region. The p-channel semiconductor active region is surrounded by the insulating layer, in the channel length direction, of the p-channel semiconductor active region and by the element isolation insulating layer, parallel to the channel length direction, of the p-channel semiconductor active region. The n-channel semiconductor active region is surrounded by the element isolation insulating layer.
摘要翻译： 半导体器件可以包括p沟道半导体有源区和n沟道半导体有源区。 元件隔离绝缘层将p沟道半导体有源区与n沟道半导体有源区电隔离。 由p沟道半导体有源区的沿其沟道长度方向与两端接触的不同材料制成的绝缘层将沟道长度方向的压缩应力施加到p沟道半导体有源区的沟道 。 p沟道半导体有源区被p沟道半导体有源区的沟道长度方向的绝缘层和与沟道长度方向平行的元件隔离绝缘层包围， 地区。 n沟道半导体有源区被元件隔离绝缘层包围。
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公开(公告)号：US08575684B2
公开(公告)日：2013-11-05
申请号：US13364602
申请日：2012-02-02
申请人： Takashi Izumida , Nobutoshi Aoki
发明人： Takashi Izumida , Nobutoshi Aoki
IPC分类号： H01L29/788 , H01L29/423
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/0688 , H01L27/11578 , H01L27/11582
摘要： In a nonvolatile semiconductor memory device provided with memory cell transistors arranged in a direction and a select transistor to select the memory cell transistors, each of the memory cell transistors of a charge trap type are at least composed of a first insulating layer and a first gate electrode respectively, and the select transistor is at least composed of a second insulating layer and a second gate electrode. The first gate electrode is provided with a first silicide layer of a first width formed on the first insulating layer. The second gate electrode is provided with an impurity-doped silicon layer formed on the second insulating layer and with a second silicide layer of a second width formed on the impurity-doped silicon layer. The second silicide has the same composition as the first silicide. The second width is larger than the first width.
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3.发明授权Semiconductor device having tri-gate structure and manufacturing method thereof 有权具有三栅结构的半导体器件及其制造方法公开(公告)号：US08258562B2
公开(公告)日：2012-09-04
申请号：US12470030
申请日：2009-05-21
IPC分类号： H01L29/76
CPC分类号： H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A semiconductor device of an example of the invention comprises a memory cell and a select gate transistor provided for the memory cell. A gate electrode of the select gate transistor has a Tri-gate structure in which an upper surface of a gate insulating film formed above a channel of the select gate transistor is set higher than a portion of an upper surface of an element isolation region of the select gate transistor.
摘要翻译： 本发明实施例的半导体器件包括为存储单元提供的存储单元和选择栅极晶体管。 选择栅极晶体管的栅电极具有三栅结构，其中形成在选择栅极晶体管的沟道上方的栅极绝缘膜的上表面被设定为高于栅极绝缘膜的元件隔离区的上表面的一部分 选择栅极晶体管。
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公开(公告)号：US08212306B2
公开(公告)日：2012-07-03
申请号：US12721757
申请日：2010-03-11
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/66825 , H01L29/7883
摘要： A semiconductor storage device has a semiconductor substrate, a plurality of first insulating films formed on the semiconductor substrate with predetermined spacing therebetween, an element isolation region formed between the first insulating films in a first direction, a floating gate electrode comprising a first charge accumulation film formed on the first insulating film, a second charge accumulation film formed on the first charge accumulation film and having a width in a second direction orthogonal to the first direction smaller than the width of the first charge accumulation film, and a third charge accumulation film formed on the second charge accumulation film and having the width in the second direction larger than the width of the second charge accumulation film, a second insulating film formed on the second charge accumulation film and between the second charge accumulation film and the element isolation region, a third insulating film formed on the charge accumulation film and the element isolation region along the second direction, and a control gate electrode formed on the third insulating film.
摘要翻译： 半导体存储装置具有半导体基板，在半导体基板上形成有规定间隔的多个第一绝缘膜，在第一方向上形成在第一绝缘膜之间的元件隔离区域，包括第一电荷累积膜的浮栅电极 形成在所述第一绝缘膜上的第二电荷累积膜，形成在所述第一电荷累积膜上并且具有与所述第一方向正交的第二方向的宽度小于所述第一电荷累积膜的宽度的第二电荷累积膜，以及形成的第三电荷累积膜 在第二电荷累积膜上并且具有大于第二电荷累积膜的宽度的第二方向的宽度，形成在第二电荷累积膜上以及在第二电荷累积膜和元件隔离区之间的第二绝缘膜， 形成在电荷累积膜上的第三绝缘膜 和沿着第二方向的元件隔离区域，以及形成在第三绝缘膜上的控制栅极电极。
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公开(公告)号：US08110864B2
公开(公告)日：2012-02-07
申请号：US12327418
申请日：2008-12-03
申请人： Takashi Izumida , Masaki Kondo
发明人： Takashi Izumida , Masaki Kondo
IPC分类号： H01L29/778
CPC分类号： H01L29/7881 , G11C16/0483 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： In one aspect of the present invention, a nonvolatile semiconductor memory device may include a semiconductor substrate; a plurality of tunnel insulating films formed on the semiconductor substrate at predetermined intervals in a first direction; a plurality of floating gate electrodes each having a first portion and a second portion, the first portions being formed on the respective tunnel insulating films, the second portions being formed on the respective first portions and having smaller width than the first portions in the first direction; an inter-gate insulating film formed on the floating gate electrodes; and first and second control gate electrodes respectively formed on sidewalls, in the first direction, of the second portion of each of the plurality of floating gate electrodes with the inter-gate insulating film interposed therebetween.
摘要翻译： 在本发明的一个方面中，非易失性半导体存储器件可以包括半导体衬底; 在第一方向上以预定间隔形成在所述半导体衬底上的多个隧道绝缘膜; 多个浮置栅极，每个具有第一部分和第二部分，所述第一部分形成在相应的隧道绝缘膜上，所述第二部分形成在相应的第一部分上，并且具有比所述第一方向上的第一部分更小的宽度 ; 形成在所述浮栅电极上的栅极间绝缘膜; 以及第一和第二控制栅极电极，分别形成在多个浮置栅电极中的每一个的第二部分的第一方向的侧壁上，栅间绝缘膜插入其间。
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6.发明申请公开(公告)号：US20110024824A1
公开(公告)日：2011-02-03
申请号：US12820351
申请日：2010-06-22
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L29/42324 , H01L27/11521 , H01L29/40114 , H01L29/66825 , H01L29/7881
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor layer and a transistor. The transistor includes: a source region, a drain region, and a channel region provided in the semiconductor layer, the channel region being between the source and drain regions; a gate insulating film provided on the channel region; a charge layer provided on the gate insulating film, the charge layer having a side portion and a apical portion;an inter-electrode insulating film covering the side portion and the apical portion; and a control gate provided on the inter-electrode insulating film. The control gate includes: a side-portion conductive layer opposing the side portion; and an apical-portion conductive layer opposing the apical portion.The apical-portion conductive layer has a work function higher than a work function of the charge layer and higher than a work function of the side-portion conductive layer.
摘要翻译： 根据一个实施例，非易失性半导体存储器件包括半导体层和晶体管。 晶体管包括：源极区，漏极区和设置在半导体层中的沟道区，沟道区位于源区和漏区之间; 设置在沟道区上的栅极绝缘膜; 设置在所述栅极绝缘膜上的电荷层，所述电荷层具有侧部和顶部; 覆盖所述侧部和所述顶部的电极间绝缘膜; 以及设置在电极间绝缘膜上的控制栅极。 控制门包括：与侧部相对的侧部导电层; 以及与顶端部分相对的顶端部导电层。 顶部导电层的功函数高于电荷层的功函数，高于侧面导电层的功函数。
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公开(公告)号：US20100207187A1
公开(公告)日：2010-08-19
申请号：US12644821
申请日：2009-12-22
申请人： Nobutoshi Aoki , Masaki Kondo , Takashi Izumida
发明人： Nobutoshi Aoki , Masaki Kondo , Takashi Izumida
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L29/40114
摘要： A nonvolatile semiconductor memory device comprises a memory cell. The memory cell includes a first gate insulating film formed on a semiconductor substrate, a floating gate formed on the first gate insulating film, a second gate insulating film formed on the floating gate, and a control gate formed on the second gate insulating film. The floating gate includes a first semiconductor film which contacts the first gate insulating film, and a metal film stacked on the semiconductor film. An effective tunneling thickness between the semiconductor substrate and the floating gate in a read operation is thicker than an effective tunneling thickness between the semiconductor substrate and the floating in a write operation.
摘要翻译： 非易失性半导体存储器件包括存储器单元。 存储单元包括形成在半导体衬底上的第一栅极绝缘膜，形成在第一栅极绝缘膜上的浮置栅极，形成在浮置栅极上的第二栅极绝缘膜，以及形成在第二栅极绝缘膜上的控制栅极。 浮置栅极包括与第一栅极绝缘膜接触的第一半导体膜和层叠在半导体膜上的金属膜。 在读取操作中，半导体衬底和浮置栅极之间的有效隧道厚度比在半导体衬底和写入操作中浮动之间的有效隧穿厚度厚。
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公开(公告)号：US20100123184A1
公开(公告)日：2010-05-20
申请号：US12618119
申请日：2009-11-13
申请人： Takashi Izumida , Nobutoshi Aoki
发明人： Takashi Izumida , Nobutoshi Aoki
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/0688 , H01L27/11578 , H01L27/11582
摘要： In a nonvolatile semiconductor memory device provided with memory cell transistors arranged in a direction and a select transistor to select the memory cell transistors, each of the memory cell transistors of a charge trap type are at least composed of a first insulating layer and a first gate electrode respectively, and the select transistor is at least composed of a second insulating layer and a second gate electrode. The first gate electrode is provided with a first silicide layer of a first width formed on the first insulating layer. The second gate electrode is provided with an impurity-doped silicon layer formed on the second insulating layer and with a second silicide layer of a second width formed on the impurity-doped silicon layer. The second silicide has the same composition as the first silicide. The second width is larger than the first width.
摘要翻译： 在设置有沿方向排列的存储单元晶体管和选择晶体管以选择存储单元晶体管的非易失性半导体存储器件中，电荷陷阱型的每个存储单元晶体管至少由第一绝缘层和第一栅极 电极，并且选择晶体管至少由第二绝缘层和第二栅电极组成。 第一栅电极设置有形成在第一绝缘层上的第一宽度的第一硅化物层。 第二栅电极设置有形成在第二绝缘层上的杂质掺杂硅层，以及形成在杂质掺杂硅层上的第二宽度的第二硅化物层。 第二硅化物具有与第一硅化物相同的组成。 第二宽度大于第一宽度。
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公开(公告)号：US08829623B2
公开(公告)日：2014-09-09
申请号：US12248483
申请日：2008-10-09
申请人： Nobutoshi Aoki , Takashi Izumida , Masaki Kondo , Fumitaka Arai
发明人： Nobutoshi Aoki , Takashi Izumida , Masaki Kondo , Fumitaka Arai
IPC分类号： H01L27/088 , H01L27/115
CPC分类号： H01L27/11529 , H01L27/11524 , H01L27/11526
摘要： According to an aspect of the present invention, there is provided a semiconductor memory device including: a semiconductor substrate having: a contact region; a select gate region; and a memory cell region; a first element isolation region formed in the contact region and having a first depth; a second element isolation region formed in the select gate region and having a second depth; and a third element isolation region formed in the memory cell region and having a third depth which is smaller than the first depth.
摘要翻译： 根据本发明的一个方面，提供了一种半导体存储器件，包括：半导体衬底，具有：接触区域; 选择栅极区; 和存储单元区域; 形成在所述接触区域中并且具有第一深度的第一元件隔离区; 形成在所述选择栅极区中并具有第二深度的第二元件隔离区; 以及形成在所述存储单元区域中并且具有小于所述第一深度的第三深度的第三元件隔离区域。
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公开(公告)号：US08610282B2
公开(公告)日：2013-12-17
申请号：US13109086
申请日：2011-05-17
IPC分类号： H01L23/13
CPC分类号： H01L23/5222 , H01L21/7682 , H01L21/76838 , H01L23/528 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a semiconductor device includes a substrate, and a plurality of interconnects provided in the same interconnect layer above the substrate. The device further includes a plurality of insulators provided so as to be buried between the plurality of interconnects. Moreover, the plurality of interconnects include an interconnect group in which 2N or more interconnects are successively arrayed so that correlation coefficients of line edge roughness (LER) between both side surfaces of the respective interconnects are positive, where N is an integer of 4 or more.
摘要翻译： 在一个实施例中，半导体器件包括衬底和设置在衬底上方的相同互连层中的多个互连。 该装置还包括多个绝缘体，其设置成埋在多个互连件之间。 此外，多个互连包括互连组，其中连续排列2N个或更多个互连，使得各互连的两个侧表面之间的线边缘粗糙度（LER）的相关系数为正，其中N为4或更大的整数 。
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