公开(公告)号：US20120019334A1

公开(公告)日：2012-01-26

申请号：US13115396

申请日：2011-05-25

申请人： Takami HIRAI ,  Masahiko Namerikawa ,  Shinsuke Yano

发明人： Takami HIRAI ,  Masahiko Namerikawa ,  Shinsuke Yano

IPC分类号： H03H7/38

CPC分类号： H03H7/38 ,  H01F17/02 ,  H01F2017/0026

摘要： The present invention intends to provide a small-sized impedance matching device with a small variation in quality and large-current tolerance. The above described intention of the present invention is achieved by an impedance matching device, which comprises a wiring portion comprising a conductor pattern for wiring, embedded inside or formed on the surface of first dielectric material, and either one or both of an inductor portion comprising a conductor pattern for inductor, embedded inside or formed on the surface of the first dielectric material, or a capacitor portion comprising at least one pair of conductor patterns for capacitor and second dielectric material with a dielectric constant larger than that of the first dielectric material, existing between the pair of conductor patterns for capacitor wherein the thicknesses of the conductor pattern for wiring and the conductor pattern for inductor are 20 μm or more.

摘要翻译： 本发明旨在提供一种具有小质量变化和大电流公差的小型阻抗匹配装置。 本发明的上述目的是通过一种阻抗匹配装置来实现的，阻抗匹配装置包括一个布线部分，该布线部分包括嵌入或形成在第一介电材料的表面上的用于布线的导体图案，以及电感器部分中的一个或两个，包括 用于电感器的导体图案，嵌入或形成在第一电介质材料的表面上，或电容器部分，其包括用于电容器的至少一对导体图案和介电常数大于第一介电材料的介电常数的第二介电材料， 存在于用于电容器的一对导体图案之间，其中用于布线的导体图案的厚度和电感器的导体图案的厚度为20μm以上。

公开(公告)号：US20110148544A1

公开(公告)日：2011-06-23

申请号：US12968758

申请日：2010-12-15

申请人： Takami HIRAI ,  Shinsuke YANO ,  Takanobu SAKA

发明人： Takami HIRAI ,  Shinsuke YANO ,  Takanobu SAKA

IPC分类号： H01P5/18

CPC分类号： H01P5/185

摘要： A directional coupler includes a dielectric substrate having at least an input terminal and an output terminal on a surface thereof, a main line disposed in the dielectric substrate and extending between the input terminal and the output terminal, a first coupling line for monitoring a level of an input signal which is input through the input terminal, the first coupling line being disposed in the dielectric substrate and having an end electrically connected to a first terminating resistor, and a second coupling line for monitoring a level of a reflected signal which is input through the output terminal, the second coupling line being disposed in the dielectric substrate and having an end electrically connected to a second terminating resistor.

摘要翻译： 定向耦合器包括：电介质基板，其至少具有输入端和在其表面上的输出端，设置在电介质基板中并在输入端和输出端之间延伸的主线;第一耦合线，用于监测电平 通过所述输入端输入的输入信号，所述第一耦合线设置在所述电介质基板中，并且具有与第一终端电阻器电连接的端部;以及第二耦合线路，用于监视通过所述输入的反射信号的电平 所述输出端子，所述第二耦合线设置在所述电介质基板中，并且具有与第二终端电阻器电连接的端部。

公开(公告)号：US20130026636A1

公开(公告)日：2013-01-31

申请号：US13237259

申请日：2011-09-20

申请人： Makoto TANI ,  Takami HIRAI ,  Shinsuke YANO ,  Tsutomu NANATAKI

发明人： Makoto TANI ,  Takami HIRAI ,  Shinsuke YANO ,  Tsutomu NANATAKI

IPC分类号： H01L23/498 ,  H05K1/09 ,  H05K1/00

CPC分类号： H01L23/49822 ,  H01L23/15 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/4629 ,  H05K2201/0191 ,  H05K2201/068 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09672 ,  H01L2924/00

摘要： A circuit board that can decrease thermal stress acting between a semiconductor element and a board in association with temperature alteration and has high mechanical strength (rigidity) as a whole board (including a multilayer wiring layer) is provided. Ceramic base material having a coefficient of thermal expansion close to that of a semiconductor element and inner layer wiring are integrally sintered, and the circuit board is configured so that fine-lined conductor structure corresponding to a multilayer wiring layer in the inner layer wiring has predetermined width, intralayer interval and interlayer interval. Thereby, thermal stress acting between a semiconductor element and the board when the board is exposed to temperature alteration in a condition where it is joined with the semiconductor element is suppressed, rigidity of the board is maintained, and its reliability against temperature cycle is increased.

摘要翻译： 提供了可以降低与温度变化相关联地在半导体元件和板之间作用的热应力并且具有作为整个板（包括多层布线层）的高机械强度（刚性）的电路板。 具有与半导体元件和内层布线接近的热膨胀系数的陶瓷基材一体烧结，并且电路板被构造成使得与内层布线中的多层布线层相对应的细线导体结构具有预定的 宽度，内膜间隔和层间间隔。 因此，抑制了在与半导体元件接合的状态下板暴露于温度变化时半导体元件与基板之间的热应力，保持板的刚性，并且提高其对温度循环的可靠性。