公开(公告)号：US4703257A

公开(公告)日：1987-10-27

申请号：US810296

申请日：1985-12-18

申请人： Takao Nishida ,  Toru Hiyama ,  Kaoru Moriwaki ,  Shun Ishiyama ,  Shunsuke Miyamoto

发明人： Takao Nishida ,  Toru Hiyama ,  Kaoru Moriwaki ,  Shun Ishiyama ,  Shunsuke Miyamoto

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318541 ,  G01R31/318536

摘要： A logic circuit having a diagnostic function is disclosed in which each of first latches for applying data to combinational circuits included in the logic circuit and/or receiving data from the combinational circuits is provided with a second latch and a selector for selecting the output of the first latch in a first mode and for selecting the output of the second latch in a second mode. In a regular operation, the output of the first latch is never transferred through the second latch, and the selector is operated in the first mode. Accordingly, the output of the first latch is supplied directly to a succeeding combinational circuit, and thus the delay caused by the second latch in the prior art can be eliminated. Although the delay caused by the selector is unavoidable, this delay can be made far smaller than the delay caused by the second latch. In a diagnostic operation, the output of the first latch is transferred through the second latch, and the selector is operated in the second mode, in order to perform the diagnostic operation stably even when data is transferred between first latches having the same phase, or the logic circuit includes a one-latch loop.

摘要翻译： 公开了一种具有诊断功能的逻辑电路，其中用于向包括在逻辑电路中的组合电路应用数据的第一锁存器和/或从组合电路接收数据中的每一个提供有第二锁存器和选择器，用于选择 第一锁存器处于第一模式并用于在第二模式中选择第二锁存器的输出。 在常规操作中，第一锁存器的输出不会通过第二锁存器传送，并且选择器在第一模式下操作。 因此，第一锁存器的输出被直接提供给后续组合电路，因此可以消除由现有技术中的第二锁存器引起的延迟。 虽然由选择器引起的延迟是不可避免的，但是该延迟可以远小于由第二锁存器引起的延迟。 在诊断操作中，第一锁存器的输出通过第二锁存器传送，并且选择器在第二模式下操作，以便即使在具有相同相位的第一锁存器之间传送数据时也可以稳定地执行诊断操作，或 逻辑电路包括单锁存环路。

公开(公告)号：US4811213A

公开(公告)日：1989-03-07

申请号：US918003

申请日：1986-10-14

申请人： Yoshio Takamine ,  Takayuki Nakagawa ,  Yoshiharu Kazama ,  Yoshiaki Kinoshita ,  Shunsuke Miyamoto

发明人： Yoshio Takamine ,  Takayuki Nakagawa ,  Yoshiharu Kazama ,  Yoshiaki Kinoshita ,  Shunsuke Miyamoto

IPC分类号： G06F17/16 ,  G06F15/78 ,  G06F15/347

CPC分类号： G06F15/8084

摘要： In response to the execution of a single loading instruction, the front half and the rear half of a designated vector may be stored in respective vector registers in a single processor operation. For this purpose, a data distribution circuit is interposed between a group of vector registers and a vector data storage for feeding the vector data read out from the storage to a first vector processor designated by an instruction without shifting and for shifting the respective components of the read-out vector data and feeding the shifted components to a second vector register designated by the instruction.

摘要翻译： 响应于单个加载指令的执行，指定向量的前半部分和后半部分可以在单个处理器操作中存储在相应的向量寄存器中。 为此，在一组向量寄存器和向量数据存储器之间插入数据分配电路，用于将从存储器读出的向量数据馈送到由指令指定的第一向量处理器，而不需要移位，并且用于将 读出向量数据并将移位的分量馈送到由指令指定的第二向量寄存器。

公开(公告)号：US4899273A

公开(公告)日：1990-02-06

申请号：US940539

申请日：1986-12-10

申请人： Koichiro Omoda ,  Shunsuke Miyamoto ,  Takayuki Nakagawa ,  Yoshio Takamine ,  Shigeo Nagashima ,  Masayuki Miyoshi ,  Yoshiharu Kazama ,  Yoshiaki Kinoshita

发明人： Koichiro Omoda ,  Shunsuke Miyamoto ,  Takayuki Nakagawa ,  Yoshio Takamine ,  Shigeo Nagashima ,  Masayuki Miyoshi ,  Yoshiharu Kazama ,  Yoshiaki Kinoshita

IPC分类号： G06F17/16 ,  G01R31/317 ,  G01R31/3173 ,  G06F17/50 ,  G06F19/00

CPC分类号： G06F17/5022 ,  G01R31/31705 ,  G01R31/3173

摘要： A computer implemented logic simulation method, for inspecting logical operations of large scale logic circuits, computes a variation of an output of at least one latch in a clock synchronized logic circuit. The clock-synchronized logic circuit contains a combination logic circuit and a plurality of logic gates. Each of the logic gates have at least one input signal and several other inputs connected to clocking signal sources of different phases. The latch is activated by the rise or fall of the clock signals for holding the output from the combination logic circuit. The method thus implements sampling instants of the output for ascertaining the logical operations of the large scale circuits.

摘要翻译： 一种用于检查大规模逻辑电路的逻辑运算的计算机实现的逻辑模拟方法，计算时钟同步逻辑电路中至少一个锁存器的输出的变化。 时钟同步逻辑电路包含组合逻辑电路和多个逻辑门。 每个逻辑门具有至少一个输入信号和几个其他输入，其连接到不同相位的时钟信号源。 锁存器由用于保持组合逻辑电路的输出的时钟信号的上升或下降而被激活。 因此，该方法实现了输出的采样时刻，以确定大规模电路的逻辑运算。

公开(公告)号：US6148909A

公开(公告)日：2000-11-21

申请号：US236371

申请日：1999-01-25

申请人： Masashi Osanai ,  Shunsuke Miyamoto ,  Tomohisa Sato ,  Hiroaki Takechi ,  Tsutomu Hatanaka ,  Norio Takahashi ,  Toshiyuki Kamei ,  Takumi Sugihara ,  Isao Shibata ,  Hironori Akiba

发明人： Masashi Osanai ,  Shunsuke Miyamoto ,  Tomohisa Sato ,  Hiroaki Takechi ,  Tsutomu Hatanaka ,  Norio Takahashi ,  Toshiyuki Kamei ,  Takumi Sugihara ,  Isao Shibata ,  Hironori Akiba

IPC分类号： F04B49/06 ,  F04B41/00 ,  F25B1/00 ,  G05D23/00 ,  G05D23/19 ,  F25B29/00

CPC分类号： G05D23/1919

摘要： A temperature control system which performs control of an object whose temperature is to be controlled as accurately as possible. The system comprises: a chiller located in a fluid circulating and supplying system, for cooling a thermal fluid returning from a vacuum chamber, a first flow control valve located in the fluid circulating and supplying system in a position between the chiller and the vacuum chamber, a bypass passage for splitting and supplying thermal fluid returning from the vacuum chamber to a position between the first flow control valve and the vacuum chamber, before it reaches the chiller, a second flow control valve located in the bypass passage, and a halogen lamp heater located in the fluid circulating and supplying system in a position between a confluence point of the bypass passage and the vacuum chamber, for adjusting the temperature of the thermal fluid passing therethrough to a set temperature.

摘要翻译： 一种温度控制系统，其对要温度控制的物体尽可能准确地进行控制。 该系统包括：位于流体循环供应系统中的冷却器，用于冷却从真空室返回的热流体;位于冷却器和真空室之间位置的流体循环供应系统中的第一流量控制阀， 旁通通道，用于将从真空室返回的热流体分流并供应到第一流量控制阀和真空室之间的位置，到达冷却器之前，位于旁路通道中的第二流量控制阀和卤素灯加热器 位于流体循环和供给系统中的位于旁路通道的汇合点和真空室之间的位置，用于将通过其的热流体的温度调节到设定温度。

公开(公告)号：US5239465A

公开(公告)日：1993-08-24

申请号：US700042

申请日：1991-05-07

申请人： Toshihiro Hattori ,  Chihei Miura ,  Shunsuke Miyamoto

发明人： Toshihiro Hattori ,  Chihei Miura ,  Shunsuke Miyamoto

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： As a basic connection information determined on the basis of a basic information determined in advance between logic elements by paying attention to the flow of data, the present invention includes a structure for transferring data from one data element to another data element, a structure for transferring data from one data element to a plurality of data elements and a structure for transferring data from a plurality of data elements to one data element, decides the sequence of unidimensional placement of sets of elements as the object of the flow of data inside a logic circuit on the basis of these structures, and automatically and quickly determine the initial placement positions of the sets of elements from the sequence thus decided.

摘要翻译： 作为基于通过注意数据流动而在逻辑元件之间预先确定的基本信息确定的基本连接信息，本发明包括将数据从一个数据元传送到另一个数据元的结构， 从一个数据元素到多个数据元素的数据和用于将数据从多个数据元素传送到一个数据元素的结构的结构，决定作为逻辑电路内的数据流的对象的一组元素的一维放置的顺序 并根据这些结构自动快速地确定元素组的初始放置位置。

公开(公告)号：US5051941A

公开(公告)日：1991-09-24

申请号：US478511

申请日：1990-02-12

申请人： Yoshio Takamine ,  Shunsuke Miyamoto ,  Takayuki Nakagawa ,  Yoshiharu Kazama ,  Yoshiaki Kinoshita

发明人： Yoshio Takamine ,  Shunsuke Miyamoto ,  Takayuki Nakagawa ,  Yoshiharu Kazama ,  Yoshiaki Kinoshita

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A method of logic simulation for simulating operation of a logic circuit by using basic signal values corresponding to states of output signals of elements of the logic circuit to be simulated and expanded signal values including the basic signal values. The logic circuit to be simulated is divided into a portion to be simulated by using the basic signal values and the expanded signal values and a portion to be simulated by using the basic signal values without using the expanded signal values. The elements for which definition of calculation method for output signal values for the input signal values including the expanded signal values is not easy are included in the latter portion, and other elements are included in the former portion. A virtual signal conversion element for converting the expanded signal into the basic signal is provided at a position where a signal is sent from the former portion to the latter portion so that the expanded signal value outputted from the element of the former portion is converted into the basic signal value before it is sent to the element of the latter portion.

摘要翻译： 一种逻辑仿真方法，用于通过使用与要被仿真的逻辑电路的元件的输出信号的状态对应的基本信号值和包括基本信号值的扩展信号值来模拟逻辑电路的操作。 要模拟的逻辑电路通过使用基本信号值和扩展信号值以及通过使用基本信号值而不使用扩展信号值而要被仿真的部分来划分为要被模拟的部分。 对于包括扩展信号值的输入信号值的输出信号值的计算方法的定义不容易的元件包括在后一部分中，并且其它元件包括在前一部分中。 将扩展信号转换为基本信号的虚拟信号转换元件设置在信号从前一部分发送到后一部分的位置，使得从前一部分的元件输出的扩展信号值被转换为 基本信号值被发送到后一部分的元素之前。

公开(公告)号：US4773006A

公开(公告)日：1988-09-20

申请号：US813007

申请日：1985-12-24

申请人： Yoshiaki Kinoshita ,  Yoshiharu Kazama ,  Shunsuke Miyamoto ,  Koichiro Omoda ,  Takayuki Nakagawa

发明人： Yoshiaki Kinoshita ,  Yoshiharu Kazama ,  Shunsuke Miyamoto ,  Koichiro Omoda ,  Takayuki Nakagawa

IPC分类号： G06F17/16 ,  G06F15/78 ,  G06F7/48 ,  G06F3/00

CPC分类号： G06F15/8053

摘要： In a vector processor for performing an operation on first and second vectors for each vector element, an operation code is set for each vector element of at least one of the first and second vectors to designate the type of an operation to be executed on the vector element, and the operation is carried out on the first and second vectors for each vector element based on the operation code.

摘要翻译： 在用于对每个向量元素执行对第一和第二向量的操作的向量处理器中，为第一和第二向量中的至少一个矢量的每个矢量元素设置操作码，以指定要在矢量上执行的操作的类型 元素，并且基于操作代码对每个向量元素的第一和第二向量执行操作。