公开(公告)号：US4899273A

公开(公告)日：1990-02-06

申请号：US940539

申请日：1986-12-10

申请人： Koichiro Omoda ,  Shunsuke Miyamoto ,  Takayuki Nakagawa ,  Yoshio Takamine ,  Shigeo Nagashima ,  Masayuki Miyoshi ,  Yoshiharu Kazama ,  Yoshiaki Kinoshita

发明人： Koichiro Omoda ,  Shunsuke Miyamoto ,  Takayuki Nakagawa ,  Yoshio Takamine ,  Shigeo Nagashima ,  Masayuki Miyoshi ,  Yoshiharu Kazama ,  Yoshiaki Kinoshita

IPC分类号： G06F17/16 ,  G01R31/317 ,  G01R31/3173 ,  G06F17/50 ,  G06F19/00

CPC分类号： G06F17/5022 ,  G01R31/31705 ,  G01R31/3173

摘要： A computer implemented logic simulation method, for inspecting logical operations of large scale logic circuits, computes a variation of an output of at least one latch in a clock synchronized logic circuit. The clock-synchronized logic circuit contains a combination logic circuit and a plurality of logic gates. Each of the logic gates have at least one input signal and several other inputs connected to clocking signal sources of different phases. The latch is activated by the rise or fall of the clock signals for holding the output from the combination logic circuit. The method thus implements sampling instants of the output for ascertaining the logical operations of the large scale circuits.

摘要翻译： 一种用于检查大规模逻辑电路的逻辑运算的计算机实现的逻辑模拟方法，计算时钟同步逻辑电路中至少一个锁存器的输出的变化。 时钟同步逻辑电路包含组合逻辑电路和多个逻辑门。 每个逻辑门具有至少一个输入信号和几个其他输入，其连接到不同相位的时钟信号源。 锁存器由用于保持组合逻辑电路的输出的时钟信号的上升或下降而被激活。 因此，该方法实现了输出的采样时刻，以确定大规模电路的逻辑运算。

公开(公告)号：US4773006A

公开(公告)日：1988-09-20

申请号：US813007

申请日：1985-12-24

申请人： Yoshiaki Kinoshita ,  Yoshiharu Kazama ,  Shunsuke Miyamoto ,  Koichiro Omoda ,  Takayuki Nakagawa

发明人： Yoshiaki Kinoshita ,  Yoshiharu Kazama ,  Shunsuke Miyamoto ,  Koichiro Omoda ,  Takayuki Nakagawa

IPC分类号： G06F17/16 ,  G06F15/78 ,  G06F7/48 ,  G06F3/00

CPC分类号： G06F15/8053

摘要： In a vector processor for performing an operation on first and second vectors for each vector element, an operation code is set for each vector element of at least one of the first and second vectors to designate the type of an operation to be executed on the vector element, and the operation is carried out on the first and second vectors for each vector element based on the operation code.

摘要翻译： 在用于对每个向量元素执行对第一和第二向量的操作的向量处理器中，为第一和第二向量中的至少一个矢量的每个矢量元素设置操作码，以指定要在矢量上执行的操作的类型 元素，并且基于操作代码对每个向量元素的第一和第二向量执行操作。

公开(公告)号：US4910667A

公开(公告)日：1990-03-20

申请号：US184788

申请日：1988-04-22

申请人： Teruo Tanaka ,  Koichiro Omoda ,  Yasuhiro Inagami ,  Takayuki Nakagawa ,  Mamoru Sugie ,  Shigeo Nagashima

发明人： Teruo Tanaka ,  Koichiro Omoda ,  Yasuhiro Inagami ,  Takayuki Nakagawa ,  Mamoru Sugie ,  Shigeo Nagashima

IPC分类号： G06F12/08 ,  G06F15/78 ,  G06F17/16

CPC分类号： G06F15/8053

摘要： In a vector processor having vector registers, a vector buffer storage for temporarily storing vector data is arranged closer to the vector registers than to a main storage, and a vector buffer storage control including an identification storage for storing identification information of the vector data stored at storage locations of the buffer storage and a check circuit for checking if the vector data identification information is in the identificatgion storage is provided. The vector buffer storage control checks if the identification information of the vector data designated by a vector data fetch instruction for the main storage is in the indentification storage, and if it is in the identification storage, it fetches the vector data from the buffer storage and transfers it to the vector register, and if it is not in the identification storage, it instructs to fetch the vector data from the main storage, transfers the vector data fetched from the main storage to the vector register and stores it into the buffer storage.

摘要翻译： 在具有向量寄存器的向量处理器中，用于临时存储向量数据的向量缓冲存储器比向主存储器靠近向量寄存器布置，并且向量缓冲器存储控制包括用于存储存储在 提供缓冲存储器的存储位置和用于检查矢量数据识别信息是否在识别存储器中的检查电路。 向量缓冲存储控制检查由主存储器的矢量数据获取指令指定的矢量数据的识别信息是否在识别存储器中，并且如果它在识别存储器中，则从缓冲存储器中取出向量数据， 将其传送到向量寄存器，如果不在识别存储器中，则指示从主存储器获取向量数据，将从主存储器获取的向量数据传送到向量寄存器，并将其存储到缓冲存储器中。

公开(公告)号：US4782441A

公开(公告)日：1988-11-01

申请号：US872396

申请日：1986-06-10

申请人： Yasuhiro Inagami ,  Shigeo Nagashima ,  Koichiro Omoda ,  Takayuki Nakagawa ,  Teruo Tanaka

发明人： Yasuhiro Inagami ,  Shigeo Nagashima ,  Koichiro Omoda ,  Takayuki Nakagawa ,  Teruo Tanaka

IPC分类号： G06F9/46 ,  G06F9/38 ,  G06F9/48 ,  G06F15/78 ,  G06F17/16 ,  G06F9/28 ,  G06F7/00

CPC分类号： G06F15/8053

摘要： In a processor such as a vector processor in which a plurality of data are processed by one instruction and a plurality of instructions are parallely processed, apparatus is provided for storing, during an interruption of the program currently being executed, the instructions being executed in the conceptual order of appearance in the program of the instruction being executed, and the sequential count of the sets of data processed. The stored information is used to restart the execution of the interrupted program at the appropriate point.

摘要翻译： 在其中通过一个指令处理多个数据并且多个指令并行处理的诸如矢量处理器的处理器中，提供装置，用于在当前执行的程序的中断期间存储在 正在执行的指令的程序中出现的概念顺序，以及处理的数据组的顺序计数。 存储的信息用于在适当的点重新启动中断的程序的执行。

公开(公告)号：US4825361A

公开(公告)日：1989-04-25

申请号：US21590

申请日：1987-03-02

申请人： Koichiro Omoda ,  Shunichi Torii ,  Shigeo Nagashima ,  Yasuhiro Inagami ,  Takayuki Nakagawa

发明人： Koichiro Omoda ,  Shunichi Torii ,  Shigeo Nagashima ,  Yasuhiro Inagami ,  Takayuki Nakagawa

IPC分类号： G06F17/16 ,  G06F15/78 ,  G06F15/347

CPC分类号： G06F15/8076

摘要： A vector processor having a vector register made up of elements of l.sub.2 -byte size for storing vector data made up of a plurality of elements read out from a main storage which has a plurality of storage areas and is capable of reading out data of l.sub.1 -byte size beginning from a specified address bound, and adapted to write vector data with an element size of m (l.sub.1 /m is an integer and l.sub.2 is larger or equal to m) into the vector register sequentially, read-out vector data from the vector register for computation by an arithmetic unit, and write the computational result into the vector register, wherein the processor writes elements of vector data read out from the main storage into separatte, specified locations of the vector register in an order required for subsequent operations.

摘要翻译： 一种矢量处理器，具有由12位字节大小的元素构成的向量寄存器，用于存储由从具有多个存储区域的主存储器读出的多个元素组成的矢量数据，并且能够读出l1- 字节大小从指定的地址限制开始，并适用于顺序地向向量寄存器中写入具有m（l1 / m为整数，l2大于或等于m）的元素大小的向量数据，从 向量寄存器，用于由算术单元计算，并将计算结果写入向量寄存器，其中处理器以从后续操作所需的顺序将从主存储器读出的向量数据的元素写入分离的向量寄存器的指定位置。

公开(公告)号：US4792893A

公开(公告)日：1988-12-20

申请号：US782534

申请日：1985-10-01

申请人： Takayuki Nakagawa ,  Koichiro Omoda

发明人： Takayuki Nakagawa ,  Koichiro Omoda

IPC分类号： G06F17/16 ,  G06F7/00 ,  G06F15/78 ,  G06F7/48

CPC分类号： G06F15/8084 ,  G06F7/00

摘要： A vector logical operation apparatus includes first and second registers respectively for sequentially receiving first and second sets of vector elements which first and second sets of vector elements are supplied in pairs on the same sequential clock periods; third register; a plurality of first gates connected to the first and third registers each for performing a first bitwise logical operation on bit signals partly provided from the first register and the third register; a plurality of second gates connected to the second register and the first gates in a bitwise manner each for performing a second bitwise logical operation on bit signals provided from the second register and the first gates; a feed back circuit connected to the plurality of second gates for supplying the outputs of the second gates to the third register; and control circuit connected to the third register for ordering the third register to receive an applied initial data signal on or before supply of a pair of the first vector element of the first set and second set and to repeatedly receive the outputs of the second gates provided by the feed back circuit on sequential clock periods each clock period being one clock period later after receipt a pair of vector elements by the first and second registers; wherein the first and second gates are operable fast enough so that the outputs of the second gates at the end of each clock period fully responds to vector elements held by the first to third registers at the beginning of each clock period.

摘要翻译： 矢量逻辑运算装置分别包括第一和第二寄存器，用于顺序地接收第一和第二组向量元素，第一和第二组矢量元素在相同的顺序时钟周期上成对提供; 第三个登记册 连接到第一和第三寄存器的多个第一门，用于对从第一寄存器和第三寄存器部分提供的位信号执行第一按位逻辑运算; 多个第二栅极，以逐位方式连接到第二寄存器和第一门，每个用于对从第二寄存器和第一门提供的位信号执行第二按位逻辑运算; 连接到所述多个第二栅极的反馈电路，用于将所述第二栅极的输出提供给所述第三寄存器; 以及连接到第三寄存器的控制电路，用于对第三寄存器进行排序，以在第一组和第二组的一对第一向量元素的供给之前或之前接收所施加的初始数据信号，并重复地接收提供的第二门的输出 通过在顺序时钟周期上的反馈电路，每个时钟周期是在由第一和第二寄存器接收到一对向量元素之后的一个时钟周期内; 其中第一和第二门可操作得足够快，使得在每个时钟周期结束时，第二门的输出在每个时钟周期的开始处完全响应由第一至第三寄存器保持的向量元素。

公开(公告)号：US5465380A

公开(公告)日：1995-11-07

申请号：US222949

申请日：1994-04-04

申请人： Naoki Hamanaka ,  Teruo Tanaka ,  Koichiro Omoda ,  Shigeo Nagashima

发明人： Naoki Hamanaka ,  Teruo Tanaka ,  Koichiro Omoda ,  Shigeo Nagashima

IPC分类号： G06F9/46 ,  G06F15/16 ,  G06F9/00

CPC分类号： G06F9/54 ,  G06F15/161

摘要： A parallel processor system which includes a plurality of processors each for executing at least one of a plurality of mutually associated programs and a transfer circuit. The transfer circuit is connected to the processors, and is provided for transferring the data outputted from any one of the programs during execution of one program by any one of the processors to other processors to which a receiving program is allotted. The transfer operation is performed in response to a program identification code outputted during execution of the one program by one processor to identify the receiving program.

摘要翻译： 一种并行处理器系统，其包括多个处理器，每个处理器用于执行多个相互关联的程序和传送电路中的至少一个。 传送电路连接到处理器，并且被提供用于将由任何一个处理器执行一个程序期间的任何一个程序输出的数据传送到分配了接收程序的其他处理器。 响应于由一个处理器执行一个程序期间输出的节目识别码来执行传送操作以识别接收节目。

公开(公告)号：US4712175A

公开(公告)日：1987-12-08

申请号：US633981

申请日：1984-07-24

申请人： Shunichi Torii ,  Shigeo Nagashima ,  Koichiro Omoda

发明人： Shunichi Torii ,  Shigeo Nagashima ,  Koichiro Omoda

IPC分类号： G06F17/16 ,  G06F9/38 ,  G06F15/78 ,  G06F15/347 ,  G06F15/16

CPC分类号： G06F15/8076 ,  G06F9/3885

摘要： A data processing apparatus comprises a plurality of sub-systems each including at least one arithmetic unit, a plurality of registers, a first selector for receiving vector data and selectively outputting the input data to the registers, and a second selector for receiving the vector data from the registers and selectively outputting the input data to a plurality of output lines. The data output of the arithmetic unit in each sub-system is supplied to the first selector in the same sub-system and the first selector in another sub-system, and the arithmetic unit in each sub-system receives the output data from the second selector in the same sub-system. The data output from the second selector in at least one sub-system is supplied to a main storage unit, and the data output from the main storage unit is supplied to the first selector in at least one sub-system.

摘要翻译： 数据处理装置包括多个子系统，每个子系统包括至少一个算术单元，多个寄存器，用于接收向量数据的第一选择器，并且将输入数据选择性地输出到寄存器;以及第二选择器，用于接收向量数据 从寄存器中选择性地将输入数据输出到多条输出线。 每个子系统中的算术单元的数据输出被提供给同一子系统中的第一选择器和另一子系统中的第一选择器，并且每个子系统中的算术单元从第二子系统接收输出数据 选择器在同一子系统中。 在至少一个子系统中从第二选择器输出的数据被提供给主存储单元，并且从主存储单元输出的数据在至少一个子系统中提供给第一选择器。

公开(公告)号：US4651274A

公开(公告)日：1987-03-17

申请号：US594301

申请日：1984-03-28

申请人： Koichiro Omoda ,  Shigeo Nagashima ,  Shunichi Torii

发明人： Koichiro Omoda ,  Shigeo Nagashima ,  Shunichi Torii

IPC分类号： G06F17/16 ,  G06F9/38 ,  G06F15/78 ,  G06F13/00 ,  G06F9/00

CPC分类号： G06F15/8084 ,  G06F9/3867

摘要： A vector data processor includes a vector index register for consecutively and sequentially storing indirect address vectors, which may then be consecutively and sequentially read out from the vector index register to form addresses of data, thereby to execute the consecutive reading of the data from a main storage and the consecutive writing thereof into the main storage with an increased processing speed by generating addresses and storing data in overlapping operations.

摘要翻译： 向量数据处理器包括一个向量索引寄存器，用于连续和顺序地存储间接地址向量，然后可以从向量索引寄存器连续地顺序地读出数据，以形成数据的地址，从而执行从主要的数据的连续读取 通过在重叠操作中生成地址和存储数据，以其增加的处理速度将其连续写入主存储器。

公开(公告)号：US5113390A

公开(公告)日：1992-05-12

申请号：US508065

申请日：1990-04-10

申请人： Takehisa Hayashi ,  Koichiro Omoda ,  Teruo Tanaka ,  Naoki Hamanaka ,  Shigeo Nagashima

发明人： Takehisa Hayashi ,  Koichiro Omoda ,  Teruo Tanaka ,  Naoki Hamanaka ,  Shigeo Nagashima

IPC分类号： H04L12/935 ,  H04L12/937

CPC分类号： H04L49/3018 ,  H04L49/254 ,  H04L49/3027

摘要： A computer system having a plurality of processors assigned first and second address portions are connected to a plurality of switch circuits. A first group transfer networks are connected to a corresponding first group of the plurality of switch circuits. Each of the transfer networks concurrently transfer data among the switch circuits. The switch circuits are provided to processors of a first kind arranged in a plurality of processor groups. The processor groups of the first kind include processors with different values for first address portions and the same value for second address portions. Additional transfer networks, processors and switches functioning in a similar manner are provided to expand the above system. In another embodiment of the present invention a data transfer network is provided having a plurality of processors for data transfer. The network includes a plurality of multistage switches each belonging to one of plural stages and connected to the switches of a preceding stage and to switches of the succeeding stage. Each of the switches are arranged to receive packets from a preceding switch. A packet includes a target process address and data to be transferred. A path select device is connected to receive packets and is also connected to plural switches belonging to a next stage for the transfer of the received partial addresses and partial data. A control device is connected to receive the partial addresses and partial data and is responsive to a predetermined bit within the received partial addresses. The control means is responsive to the arrival of the first partial address of the packet.