公开(公告)号：US08354706B2

公开(公告)日：2013-01-15

申请号：US12719193

申请日：2010-03-08

申请人： Takahisa Kanemura ,  Tomomi Kusaka ,  Takashi Izumida ,  Masaki Kondo ,  Nobutoshi Aoki

发明人： Takahisa Kanemura ,  Tomomi Kusaka ,  Takashi Izumida ,  Masaki Kondo ,  Nobutoshi Aoki

IPC分类号： H01L29/788

CPC分类号： H01L29/7883 ,  G11C16/0441 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324

摘要： A semiconductor memory device according to an embodiment of the present invention includes a substrate, a first gate insulator formed on the substrate and serving as an F-N (Fowler-Nordheim) tunneling film, a first floating gate formed on the first gate insulator, a second gate insulator formed on the first floating gate and serving as an F-N tunneling film, a second floating gate formed on the second gate insulator, an intergate insulator formed on the second floating gate and serving as a charge blocking film, and a control gate formed on the intergate insulator, at least one of the first and second floating gates including a metal layer.

摘要翻译： 根据本发明实施例的半导体存储器件包括衬底，形成在衬底上并用作FN（Fowler-Nordheim）隧穿膜的第一栅极绝缘体，形成在第一栅绝缘体上的第一浮栅，第二栅绝缘体 形成在第一浮栅上并用作FN隧穿膜的栅极绝缘体，形成在第二栅极绝缘体上的第二浮栅，形成在第二浮栅上并用作电荷阻挡膜的栅极绝缘体，以及形成在栅极绝缘体上的控制栅极 所述隔间绝缘体，所述第一和第二浮动栅极中的至少一个包括金属层。

公开(公告)号：US08289782B2

公开(公告)日：2012-10-16

申请号：US12719420

申请日：2010-03-08

申请人： Takashi Izumida ,  Tomomi Kusaka ,  Masaki Kondo ,  Nobutoshi Aoki

发明人： Takashi Izumida ,  Tomomi Kusaka ,  Masaki Kondo ,  Nobutoshi Aoki

IPC分类号： G11C16/04

CPC分类号： H01L29/7881 ,  G11C16/0408 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11531 ,  H01L29/42332 ,  H01L29/7887

摘要： A semiconductor memory device according to an embodiment of the present invention includes a substrate, a gate insulator formed on the substrate and serving as an F-N (Fowler-Nordheim) tunneling film, a first floating gate formed on the gate insulator, a first intergate insulator formed on the first floating gate and serving as an F-N tunneling film, a second floating gate formed on the first intergate insulator, a second intergate insulator formed on the second floating gate and serving as a charge blocking film, and a control gate formed on the second intergate insulator.

摘要翻译： 根据本发明的实施例的半导体存储器件包括：衬底，形成在衬底上并用作FN（Fowler-Nordheim）隧穿膜的栅极绝缘体，形成在栅极绝缘体上的第一浮栅，第一栅极绝缘体 形成在第一浮栅上并用作FN隧道膜，形成在第一栅极绝缘体上的第二浮栅，形成在第二浮栅上并用作电荷阻挡膜的第二栅极绝缘体，以及形成在第一浮栅上的控制栅 第二隔间绝缘子。

公开(公告)号：US20110122698A1

公开(公告)日：2011-05-26

申请号：US12719420

申请日：2010-03-08

申请人： Takashi IZUMIDA ,  Tomomi Kusaka ,  Masaki Kondo ,  Nobutoshi Aoki

发明人： Takashi IZUMIDA ,  Tomomi Kusaka ,  Masaki Kondo ,  Nobutoshi Aoki

IPC分类号： G11C16/04 ,  H01L29/792

CPC分类号： H01L29/7881 ,  G11C16/0408 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11531 ,  H01L29/42332 ,  H01L29/7887

摘要： A semiconductor memory device according to an embodiment of the present invention includes a substrate, a gate insulator formed on the substrate and serving as an F-N (Fowler-Nordheim) tunneling film, a first floating gate formed on the gate insulator, a first intergate insulator formed on the first floating gate and serving as an F-N tunneling film, a second floating gate formed on the first intergate insulator, a second intergate insulator formed on the second floating gate and serving as a charge blocking film, and a control gate formed on the second intergate insulator.

摘要翻译： 根据本发明的实施例的半导体存储器件包括：衬底，形成在衬底上并用作FN（Fowler-Nordheim）隧穿膜的栅极绝缘体，形成在栅极绝缘体上的第一浮栅，第一栅极绝缘体 形成在第一浮栅上并用作FN隧道膜，形成在第一栅极绝缘体上的第二浮栅，形成在第二浮栅上并用作电荷阻挡膜的第二栅极绝缘体，以及形成在第一浮栅上的控制栅 第二隔间绝缘子。

公开(公告)号：US08421142B2

公开(公告)日：2013-04-16

申请号：US12886160

申请日：2010-09-20

申请人： Noboru Ooike ,  Tomomi Kusaka

发明人： Noboru Ooike ,  Tomomi Kusaka

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/7881 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/76224 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/66825

摘要： In one embodiment, a nonvolatile semiconductor memory device includes a substrate, and a well region formed in the substrate. The device further includes device regions formed in the well region and defined by isolation trenches formed in the well region, the device regions extending in a first direction parallel to a principal surface of the substrate, and being adjacent to one another in a second direction that is perpendicular to the first direction. The device further includes isolation insulators buried in the isolation trenches to isolate the device regions from one another. The device further includes floating gates disposed on the device regions via gate insulators, and a control gate disposed on the floating gates via an intergate insulator. The device further includes first diffusion suppressing layers formed inside the respective device regions to divide each of the device regions into an upper device region and a lower device region. The device further includes second diffusion suppressing layers formed on side surfaces of the respective upper device regions, the side surfaces being perpendicular to the second direction.

摘要翻译： 在一个实施例中，非易失性半导体存储器件包括衬底和形成在衬底中的阱区。 该器件还包括形成在阱区中并由形成在阱区中的隔离沟槽限定的器件区，器件区沿平行于衬底的主表面的第一方向延伸，并在第二方向彼此相邻地延伸， 垂直于第一方向。 该器件还包括埋在隔离沟槽中的隔离绝缘体，以将器件区域彼此隔离。 该器件还包括经由栅极绝缘体设置在器件区域上的浮动栅极和经由栅极绝缘体设置在浮置栅极上的控制栅极。 该器件还包括形成在各个器件区域内部的第一扩散抑制层，以将每个器件区域分成上部器件区域和下部器件区域。 该装置还包括形成在各个上部装置区域的侧表面上的第二扩散抑制层，该侧表面垂直于该第二方向。

公开(公告)号：US20100178757A1

公开(公告)日：2010-07-15

申请号：US12614912

申请日：2009-11-09

申请人： Tomomi Kusaka ,  Takahisa Kanemura

发明人： Tomomi Kusaka ,  Takahisa Kanemura

IPC分类号： H01L21/265 ,  G06F19/00

CPC分类号： H01L21/2236 ,  H01J37/32412

摘要： A process simulation method includes: converting condition data of plasma doping for introducing an impurity into a semiconductor in a plasma atmosphere to corresponding condition data of ion implantation for implanting impurities as an ion beam into the semiconductor; and calculating device structure data on the basis of the ion implantation condition data converted from the plasma doping condition data.

摘要翻译： 一种过程模拟方法包括：将等离子体掺杂的条件数据转换成等离子体气氛中的半导体中的等离子体掺杂物，作为离子注入的对应条件数据，将作为离子束的杂质注入到半导体中; 以及基于从等离子体掺杂条件数据转换的离子注入条件数据来计算器件结构数据。

公开(公告)号：US20110291174A1

公开(公告)日：2011-12-01

申请号：US12886160

申请日：2010-09-20

申请人： Noboru OOIKE ,  Tomomi Kusaka

发明人： Noboru OOIKE ,  Tomomi Kusaka

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/7881 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/76224 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/66825

摘要： In one embodiment, a nonvolatile semiconductor memory device includes a substrate, and a well region formed in the substrate. The device further includes device regions formed in the well region and defined by isolation trenches formed in the well region, the device regions extending in a first direction parallel to a principal surface of the substrate, and being adjacent to one another in a second direction that is perpendicular to the first direction. The device further includes isolation insulators buried in the isolation trenches to isolate the device regions from one another. The device further includes floating gates disposed on the device regions via gate insulators, and a control gate disposed on the floating gates via an intergate insulator. The device further includes first diffusion suppressing layers formed inside the respective device regions to divide each of the device regions into an upper device region and a lower device region. The device further includes second diffusion suppressing layers formed on side surfaces of the respective upper device regions, the side surfaces being perpendicular to the second direction.

摘要翻译： 在一个实施例中，非易失性半导体存储器件包括衬底和形成在衬底中的阱区。 该器件还包括形成在阱区中并由形成在阱区中的隔离沟槽限定的器件区，器件区沿平行于衬底的主表面的第一方向延伸，并在第二方向彼此相邻地延伸， 垂直于第一方向。 该器件还包括埋在隔离沟槽中的隔离绝缘体，以将器件区域彼此隔离。 该器件还包括经由栅极绝缘体设置在器件区域上的浮动栅极和经由栅极绝缘体设置在浮置栅极上的控制栅极。 该器件还包括形成在各个器件区域内部的第一扩散抑制层，以将每个器件区域分成上部器件区域和下部器件区域。 该装置还包括形成在各个上部装置区域的侧表面上的第二扩散抑制层，该侧表面垂直于该第二方向。

公开(公告)号：US07972944B2

公开(公告)日：2011-07-05

申请号：US12614912

申请日：2009-11-09

申请人： Tomomi Kusaka ,  Takahisa Kanemura

发明人： Tomomi Kusaka ,  Takahisa Kanemura

IPC分类号： H01L21/26 ,  H01L21/42

CPC分类号： H01L21/2236 ,  H01J37/32412

摘要： A process simulation method includes: converting condition data of plasma doping for introducing an impurity into a semiconductor in a plasma atmosphere to corresponding condition data of ion implantation for implanting impurities as an ion beam into the semiconductor; and calculating device structure data on the basis of the ion implantation condition data converted from the plasma doping condition data.

摘要翻译： 一种过程模拟方法包括：将等离子体掺杂的条件数据转换成等离子体气氛中的半导体中的等离子体掺杂物，作为离子注入的对应条件数据，将作为离子束的杂质注入到半导体中; 以及基于从等离子体掺杂条件数据转换的离子注入条件数据来计算器件结构数据。

公开(公告)号：US20110231174A1

公开(公告)日：2011-09-22

申请号：US13116317

申请日：2011-05-26

申请人： Tomomi Kusaka ,  Takahisa Kanemura

发明人： Tomomi Kusaka ,  Takahisa Kanemura

IPC分类号： G06G7/62

CPC分类号： H01L21/2236 ,  H01J37/32412

摘要： A process simulation method includes: converting condition data of plasma doping for introducing an impurity into a semiconductor in a plasma atmosphere to corresponding condition data of ion implantation for implanting impurities as an ion beam into the semiconductor; and calculating device structure data on the basis of the ion implantation condition data converted from the plasma doping condition data.

摘要翻译： 一种过程模拟方法包括：将等离子体掺杂的条件数据转换成等离子体气氛中的半导体中的等离子体掺杂物，作为离子注入的对应条件数据，将作为离子束的杂质注入到半导体中; 以及基于从等离子体掺杂条件数据转换的离子注入条件数据来计算器件结构数据。