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    Nonvolatile semiconductor memory device having assist gate
    1.
    发明申请
    Nonvolatile semiconductor memory device having assist gate 失效
    具有辅助门的非易失性半导体存储器件

    公开(公告)号：US20060280022A1

    公开(公告)日：2006-12-14

    申请号：US11411938

    申请日：2006-04-27

    申请人： Takashi Kono ,  Yuichi Kunori ,  Hironori Iga

    发明人： Takashi Kono ,  Yuichi Kunori ,  Hironori Iga

    IPC分类号： G11C8/00

    CPC分类号： G11C16/0491 ,  G11C16/0433 ,  G11C16/24 ,  G11C16/26

    摘要： In this AG-AND type flash memory, a layered bit line configuration where a memory array is divided into a plurality of sub blocks, new main bit lines are allocated so as to correspond to each sub block, and a main bit line is selectively connected to a global bit line in an upper layer via a switch is adopted, so that charge sharing write-in is carried out between two main bit lines. Accordingly, write-in of data into the flash memory can be carried out with low power consumption, and the threshold voltage can be controlled with precision.

    摘要翻译： 在该AG-AND型闪存中，分层位线配置将存储器阵列分成多个子块，分配新的主位线以便对应于每个子块，并且主位线被选择性地连接 采用通过开关在上层的全局位线，从而在两个主位线之间执行电荷共享写入。 因此，可以以低功耗进行数据写入闪速存储器，并且可以精确地控制阈值电压。

    Semiconductor memory device capable of operating at high speed and with low power consumption while ensuring reliability of memory cell
    2.
    发明授权
    Semiconductor memory device capable of operating at high speed and with low power consumption while ensuring reliability of memory cell 失效
    半导体存储器件能够在确保存储单元的可靠性的同时以高速和低功耗运行

    公开(公告)号：US07102953B2

    公开(公告)日：2006-09-05

    申请号：US11030185

    申请日：2005-01-07

    申请人： Takashi Kono ,  Hironori Iga

    发明人： Takashi Kono ,  Hironori Iga

    IPC分类号： G11C5/14

    CPC分类号： G11C29/021 ,  G11C5/147 ,  G11C11/401 ,  G11C11/4074 ,  G11C29/02 ,  G11C29/028 ,  G11C2029/5004 ,  G11C2207/2227

    摘要： A monitor circuit for monitoring external potential EXTVDD and variable delay circuit determine the time interval in which signal ZODACT is being at the L level according to the potential level of external potential EXTVDD, and thus the supplying time of external potential EXTVDD can be dynamically changed. When external potential EXTVDD is at the upper limit of specification of product, the supplying time is short, thereby preventing overcharge of memory cells or bit lines. When external potential EXTVDD is at the lower limit of specification of product, the supplying time becomes longer, thereby ensuring a sufficient over-driving time interval. It is possible to ensure the reliability of the memory cells and perform the reading operation throughout the entire range of the specification of product of external potential EXTVDD. Therefore, it is possible to provide a semiconductor memory device capable of performing a reading operation at high speeds while ensuring the reliability.

    摘要翻译： 用于监视外部电位EXTVDD和可变延迟电路的监视电路根据外部电位EXTVDD的电位电平确定信号ZODACT处于L电平的时间间隔，从而可以动态地改变外部电位EXTVDD的供电时间。 当外部电位EXTVDD处于产品规格的上限时，供电时间短，从而防止存储单元或位线的过充电。 当外部电位EXTVDD处于产品规格的下限时，供电时间变长，从而确保足够的过驱动时间间隔。 可以确保存储单元的可靠性，并在外部电位EXTVDD的产品规格的整个范围内执行读取操作。 因此，可以提供能够在确保可靠性的同时高速执行读取操作的半导体存储器件。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING ASSIST GATE
    3.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING ASSIST GATE 有权
    具有辅助门的非易失性半导体存储器件

    公开(公告)号：US20100142279A1

    公开(公告)日：2010-06-10

    申请号：US12705357

    申请日：2010-02-12

    申请人： Takashi Kono ,  Yuichi Kunori ,  Hironori Iga

    发明人： Takashi Kono ,  Yuichi Kunori ,  Hironori Iga

    IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C7/06

    CPC分类号： G11C16/0491 ,  G11C16/0433 ,  G11C16/24 ,  G11C16/26

    摘要： In this AG-AND type flash memory, a layered bit line configuration where a memory array is divided into a plurality of sub blocks, new main bit lines are allocated so as to correspond to each sub block, and a main bit line is selectively connected to a global bit line in an upper layer via a switch is adopted, so that charge sharing write-in is carried out between two main bit lines. Accordingly, write-in of data into the flash memory can be carried out with low power consumption, and the threshold voltage can be controlled with precision.

    摘要翻译： 在该AG-AND型闪存中，分层位线配置将存储器阵列分成多个子块，分配新的主位线以便对应于每个子块，并且主位线被选择性地连接 采用通过开关在上层的全局位线，从而在两个主位线之间执行电荷共享写入。 因此，可以以低功耗进行数据写入闪速存储器，并且可以精确地控制阈值电压。

    Semiconductor memory device capable of operating at high speed and with low power consumption while ensuring reliability of memory cell
    4.
    发明申请
    Semiconductor memory device capable of operating at high speed and with low power consumption while ensuring reliability of memory cell 失效
    半导体存储器件能够在确保存储单元的可靠性的同时以高速和低功耗运行

    公开(公告)号：US20050169087A1

    公开(公告)日：2005-08-04

    申请号：US11030185

    申请日：2005-01-07

    申请人： Takashi Kono ,  Hironori Iga

    发明人： Takashi Kono ,  Hironori Iga

    IPC分类号： G11C11/407 ,  G11C5/00 ,  G11C5/14 ,  G11C7/06 ,  G11C11/34 ,  G11C11/4074 ,  G11C29/02

    CPC分类号： G11C29/021 ,  G11C5/147 ,  G11C11/401 ,  G11C11/4074 ,  G11C29/02 ,  G11C29/028 ,  G11C2029/5004 ,  G11C2207/2227

    摘要： A monitor circuit for monitoring external potential EXTVDD and variable delay circuit determine the time interval in which signal ZODACT is being at the L level according to the potential level of external potential EXTVDD, and thus the supplying time of external potential EXTVDD can be dynamically changed. When external potential EXTVDD is at the upper limit of specification of product, the supplying time is short, thereby preventing overcharge of memory cells or bit lines. When external potential EXTVDD is at the lower limit of specification of product, the supplying time becomes longer, thereby ensuring a sufficient over-driving time interval. It is possible to ensure the reliability of the memory cells and perform the reading operation throughout the entire range of the specification of product of external potential EXTVDD. Therefore, it is possible to provide a semiconductor memory device capable of performing a reading operation at high speeds while ensuring the reliability.

    摘要翻译： 用于监视外部电位EXTVDD和可变延迟电路的监视电路根据外部电位EXTVDD的电位电平确定信号ZODACT处于L电平的时间间隔，从而可以动态地改变外部电位EXTVDD的供电时间。 当外部电位EXTVDD处于产品规格的上限时，供电时间短，从而防止存储单元或位线的过充电。 当外部电位EXTVDD处于产品规格的下限时，供电时间变长，从而确保足够的过驱动时间间隔。 可以确保存储单元的可靠性，并在外部电位EXTVDD的产品规格的整个范围内执行读取操作。 因此，可以提供能够在确保可靠性的同时高速执行读取操作的半导体存储器件。

    Nonvolatile semiconductor memory device having assist gate
    6.
    发明授权
    Nonvolatile semiconductor memory device having assist gate 有权
    具有辅助门的非易失性半导体存储器件

    公开(公告)号：US07952926B2

    公开(公告)日：2011-05-31

    申请号：US12705357

    申请日：2010-02-12

    申请人： Takashi Kono ,  Yuichi Kunori ,  Hironori Iga

    发明人： Takashi Kono ,  Yuichi Kunori ,  Hironori Iga

    IPC分类号： G11C11/34

    CPC分类号： G11C16/0491 ,  G11C16/0433 ,  G11C16/24 ,  G11C16/26

    摘要： In this AG-AND type flash memory, a layered bit line configuration where a memory array is divided into a plurality of sub blocks, new main bit lines are allocated so as to correspond to each sub block, and a main bit line is selectively connected to a global bit line in an upper layer via a switch is adopted, so that charge sharing write-in is carried out between two main bit lines. Accordingly, write-in of data into the flash memory can be carried out with low power consumption, and the threshold voltage can be controlled with precision.

    摘要翻译： 在该AG-AND型闪存中，分层位线配置将存储器阵列分成多个子块，分配新的主位线以便对应于每个子块，并且主位线被选择性地连接 采用通过开关在上层的全局位线，从而在两个主位线之间执行电荷共享写入。 因此，可以以低功耗进行数据写入闪速存储器，并且可以精确地控制阈值电压。

    Nonvolatile semiconductor memory device having assist gate
    7.
    发明授权
    Nonvolatile semiconductor memory device having assist gate 有权
    具有辅助门的非易失性半导体存储器件

    公开(公告)号：US07692966B2

    公开(公告)日：2010-04-06

    申请号：US12153927

    申请日：2008-05-28

    申请人： Takashi Kono ,  Yuichi Kunori ,  Hironori Iga

    发明人： Takashi Kono ,  Yuichi Kunori ,  Hironori Iga

    IPC分类号： G11C11/34 ,  G11C8/00

    CPC分类号： G11C16/0491 ,  G11C16/0433 ,  G11C16/24 ,  G11C16/26

    摘要： In this AG-AND type flash memory, a layered bit line configuration where a memory array is divided into a plurality of sub blocks, new main bit lines are allocated so as to correspond to each sub block, and a main bit line is selectively connected to a global bit line in an upper layer via a switch is adopted, so that charge sharing write-in is carried out between two main bit lines. Accordingly, write-in of data into the flash memory can be carried out with low power consumption, and the threshold voltage can be controlled with precision.

    摘要翻译： 在该AG-AND型闪存中，分层位线配置将存储器阵列分成多个子块，分配新的主位线以便对应于每个子块，并且主位线被选择性地连接 采用通过开关在上层的全局位线，从而在两个主位线之间执行电荷共享写入。 因此，可以以低功耗进行数据写入闪速存储器，并且可以精确地控制阈值电压。

    Nonvolatile semiconductor memory device having assist gate
    8.
    发明授权
    Nonvolatile semiconductor memory device having assist gate 失效
    具有辅助门的非易失性半导体存储器件

    公开(公告)号：US07433230B2

    公开(公告)日：2008-10-07

    申请号：US11411938

    申请日：2006-04-27

    申请人： Takashi Kono ,  Yuichi Kunori ,  Hironori Iga

    发明人： Takashi Kono ,  Yuichi Kunori ,  Hironori Iga

    IPC分类号： G11C11/34 ,  G11C5/06 ,  G11C7/00 ,  G11C8/99

    CPC分类号： G11C16/0491 ,  G11C16/0433 ,  G11C16/24 ,  G11C16/26

    摘要： In this AG-AND type flash memory, a layered bit line configuration where a memory array is divided into a plurality of sub blocks, new main bit lines are allocated so as to correspond to each sub block, and a main bit line is selectively connected to a global bit line in an upper layer via a switch is adopted, so that charge sharing write-in is carried out between two main bit lines. Accordingly, write-in of data into the flash memory can be carried out with low power consumption, and the threshold voltage can be controlled with precision.

    摘要翻译： 在该AG-AND型闪存中，分层位线配置将存储器阵列分成多个子块，分配新的主位线以便对应于每个子块，并且主位线被选择性地连接 采用通过开关在上层的全局位线，从而在两个主位线之间执行电荷共享写入。 因此，可以以低功耗进行数据写入闪速存储器，并且可以精确地控制阈值电压。

    Semiconductor memory device capable of operating at high speed and with low power consumption while ensuring reliability of memory cell
    9.
    发明授权
    Semiconductor memory device capable of operating at high speed and with low power consumption while ensuring reliability of memory cell 失效

    公开(公告)号：US07154802B2

    公开(公告)日：2006-12-26

    申请号：US11493663

    申请日：2006-07-27

    申请人： Takashi Kono ,  Hironori Iga

    发明人： Takashi Kono ,  Hironori Iga

    IPC分类号： G11C5/14

    CPC分类号： G11C29/021 ,  G11C5/147 ,  G11C11/401 ,  G11C11/4074 ,  G11C29/02 ,  G11C29/028 ,  G11C2029/5004 ,  G11C2207/2227

    摘要： A monitor circuit for monitoring external potential EXTVDD and variable delay circuit determine the time interval in which signal ZODACT is being at the L level according to the potential level of external potential EXTVDD, and thus the supplying time of external potential EXTVDD can be dynamically changed. When external potential EXTVDD is at the upper limit of specification of product, the supplying time is short, thereby preventing overcharge of memory cells or bit lines. When external potential EXTVDD is at the lower limit of specification of product, the supplying time becomes longer, thereby ensuring a sufficient over-driving time interval. It is possible to ensure the reliability of the memory cells and perform the reading operation throughout the entire range of the specification of product of external potential EXTVDD. Therefore, it is possible to provide a semiconductor memory device capable of performing a reading operation at high speeds while ensuring the reliability.

    SEMICONDUCTOR MEMORY DEVICE CAPABLE OF OPERATING AT HIGH SPEED AND WITH LOW POWER CONSUMPTION WHILE ENSURING RELIABILITY OF MEMORY CELL
    10.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE CAPABLE OF OPERATING AT HIGH SPEED AND WITH LOW POWER CONSUMPTION WHILE ENSURING RELIABILITY OF MEMORY CELL 失效
    半导体存储器件，能够在高速和低功耗的情况下工作，同时保持存储单元的可靠性

    公开(公告)号：US20060262629A1

    公开(公告)日：2006-11-23

    申请号：US11493663

    申请日：2006-07-27

    申请人： Takashi Kono ,  Hironori Iga

    发明人： Takashi Kono ,  Hironori Iga

    IPC分类号： G11C5/14

    CPC分类号： G11C29/021 ,  G11C5/147 ,  G11C11/401 ,  G11C11/4074 ,  G11C29/02 ,  G11C29/028 ,  G11C2029/5004 ,  G11C2207/2227

    摘要： A monitor circuit for monitoring external potential EXTVDD and variable delay circuit determine the time interval in which signal ZODACT is being at the L level according to the potential level of external potential EXTVDD, and thus the supplying time of external potential EXTVDD can be dynamically changed. When external potential EXTVDD is at the upper limit of specification of product, the supplying time is short, thereby preventing overcharge of memory cells or bit lines. When external potential EXTVDD is at the lower limit of specification of product, the supplying time becomes longer, thereby ensuring a sufficient over-driving time interval. It is possible to ensure the reliability of the memory cells and perform the reading operation throughout the entire range of the specification of product of external potential EXTVDD. Therefore, it is possible to provide a semiconductor memory device capable of performing a reading operation at high speeds while ensuring the reliability.

    摘要翻译： 用于监视外部电位EXTVDD和可变延迟电路的监视电路根据外部电位EXTVDD的电位电平确定信号ZODACT处于L电平的时间间隔，因此可以动态地改变外部电位EXTVDD的供电时间。 当外部电位EXTVDD处于产品规格的上限时，供电时间短，从而防止存储单元或位线的过充电。 当外部电位EXTVDD处于产品规格的下限时，供电时间变长，从而确保足够的过驱动时间间隔。 可以确保存储单元的可靠性，并在外部电位EXTVDD的产品规格的整个范围内执行读取操作。 因此，可以提供能够在确保可靠性的同时高速执行读取操作的半导体存储器件。