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公开(公告)号：US08043918B2
公开(公告)日：2011-10-25
申请号：US12840430
申请日：2010-07-21
IPC分类号： H01L21/336
CPC分类号： H01L21/823475 , H01L21/743 , H01L21/76229 , H01L21/763 , H01L21/823481 , H01L21/823871 , H01L21/823878 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： To manufacture in high productivity a semiconductor device capable of securely achieving element isolation by a trench-type element isolation and capable of effectively preventing potentials of adjacent elements from affecting other nodes, a method of manufacturing the semiconductor device includes: a step of forming a first layer on a substrate; a step of forming a trench by etching the first layer and the substrate; a step of thermally oxidizing an inner wall of the trench; a step of depositing a first conductive film having a film thickness equal to or larger than one half of the trench width of the trench on the substrate including the trench; a step of removing a first conductive film from the first layer by a CMP method and keeping the first conductive film left in only the trench; a step of anisotropically etching the first conductive film within the trench to adjust the height of the conductive film to become lower than the height of the surface of the substrate; a step of depositing an insulating film on the first conductive film by the CVD method to embed the upper part of the first conductive film within the trench; a step of flattening the insulating film by the CMP method; and a step of removing the first layer.
摘要翻译： 为了以高生产率制造能够通过沟槽型元件隔离可靠地实现元件隔离并且能够有效地防止相邻元件的电位影响其他节点的半导体器件，制造半导体器件的方法包括：形成第一 层; 通过蚀刻第一层和衬底形成沟槽的步骤; 热氧化沟槽内壁的步骤; 在包括沟槽的衬底上沉积膜厚度等于或大于沟槽的沟槽宽度的一半的第一导电膜的步骤; 通过CMP方法从第一层除去第一导电膜并保持第一导电膜仅留在沟槽中的步骤; 在沟槽内各向异性蚀刻第一导电膜的步骤，以调节导电膜的高度，使其低于衬底表面的高度; 通过CVD法在第一导电膜上沉积绝缘膜以将第一导电膜的上部嵌入沟槽内的步骤; 通过CMP方法使绝缘膜平坦化的步骤; 以及去除第一层的步骤。
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公开(公告)号：US07791163B2
公开(公告)日：2010-09-07
申请号：US11577878
申请日：2005-10-18
IPC分类号： H01L29/768
CPC分类号： H01L21/823475 , H01L21/743 , H01L21/76229 , H01L21/763 , H01L21/823481 , H01L21/823871 , H01L21/823878 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： In the process of manufacturing a semiconductor device, a first layer is formed on a substrate, and the first layer and the substrate are etched to form a trench. The inner wall of the trench is thermally oxidized. On the substrate, including inside the trench, is deposited a first conductive film having a thickness equal to or larger than one half of the width of the trench. The first conductive film on the first layer is removed by chemical mechanical polishing such that the first conductive film remains in only the trench. The height of the first conductive film in the trench is adjusted to be lower than a surface of the substrate by anisotropically etching the first conductive film. An insulating film is deposited on the substrate by chemical vapor deposition to cover an upper surface of the first conductive film in the trench. The insulating film is flattened by chemical mechanical polishing, and the first layer is removed.
摘要翻译： 在制造半导体器件的过程中，在衬底上形成第一层，并且蚀刻第一层和衬底以形成沟槽。 沟槽的内壁被热氧化。 在包括沟槽内部的衬底上沉积厚度等于或大于沟槽宽度的一半的第一导电膜。 通过化学机械抛光去除第一层上的第一导电膜，使得第一导电膜仅保留在沟槽中。 通过各向异性蚀刻第一导电膜，将沟槽中的第一导电膜的高度调节为低于衬底的表面。 通过化学气相沉积在衬底上沉积绝缘膜以覆盖沟槽中的第一导电膜的上表面。 绝缘膜通过化学机械抛光而变平，第一层被去除。
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公开(公告)号：US20070241373A1
公开(公告)日：2007-10-18
申请号：US11577878
申请日：2005-10-18
IPC分类号： H01L29/768 , H01L21/76 , H01L29/00
CPC分类号： H01L21/823475 , H01L21/743 , H01L21/76229 , H01L21/763 , H01L21/823481 , H01L21/823871 , H01L21/823878 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： In the process of manufacturing a semiconductor device, a first layer is formed on a substrate, and the first layer and the substrate are etched to form a trench. The inner wall of the trench is thermally oxidized. On the substrate, including inside the trench, is deposited a first conductive film having a thickness equal to or larger than one half of the width of the trench. The first conductive film on the first layer is removed by chemical mechanical polishing such that the first conductive film remains in only the trench. The height of the first conductive film in the trench is adjusted to be lower than a surface of the substrate by anisotropically etching the first conductive film. An insulating film is deposited on the substrate by chemical vapor deposition to cover an upper surface of the first conductive film in the trench. The insulating film is flattened by chemical mechanical polishing, and the first layer is removed.
摘要翻译： 在制造半导体器件的过程中，在衬底上形成第一层，并且蚀刻第一层和衬底以形成沟槽。 沟槽的内壁被热氧化。 在包括沟槽内部的衬底上沉积厚度等于或大于沟槽宽度的一半的第一导电膜。 通过化学机械抛光去除第一层上的第一导电膜，使得第一导电膜仅保留在沟槽中。 通过各向异性蚀刻第一导电膜，将沟槽中的第一导电膜的高度调节为低于衬底的表面。 通过化学气相沉积在衬底上沉积绝缘膜以覆盖沟槽中的第一导电膜的上表面。 绝缘膜通过化学机械抛光而变平，第一层被去除。
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公开(公告)号：US06667221B2
公开(公告)日：2003-12-23
申请号：US10212274
申请日：2002-08-06
IPC分类号： H01L2176
CPC分类号： H01L23/544 , H01L21/3081 , H01L21/76229 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： A technique for preventing a decrease in alignment accuracy during a photolithography process is provided. A substrate (1) is prepared, in the surface (80) of which trenches (7) for use as alignment marks and trenches (17, 27) each forming an element isolation structure are formed and on the surface (80) of which a polysilicon film (3) is formed, avoiding the trenches (7, 17, 27). The trenches (7, 17, 27) are filled with an insulation film (30). The insulation film (30) is then selectively etched to partially remove the insulation film (30) in the trenches (7) and to leave the insulation film (30) on side and bottom surfaces (81, 82) of the trenches (7). Using the insulation film (30) in the trenches (7) as a protective film, the polysilicon film (3) is selectively etched. The use of the insulation film (30) in the trenches (7) as a protective film prevents the substrate (1) from being etched and thereby prevents the shape of the trenches (7) from being changed. This results in prevention of a decrease in alignment accuracy during a photolithography process.
摘要翻译： 提供了一种在光刻工艺中防止对准精度降低的技术。 在表面（80）中制备基板（1），其中形成用作对准标记的沟槽（7）和形成元件隔离结构的沟槽（17,27），并且其表面（80） 形成多晶硅膜（3），避免了沟槽（7,17,27）。 沟槽（7,17,27）填充绝缘膜（30）。 然后选择性地蚀刻绝缘膜（30）以部分去除沟槽（7）中的绝缘膜（30）并且在沟槽（7）的侧面和底面（81,82）上留下绝缘膜（30） 。 使用沟槽（7）中的绝缘膜（30）作为保护膜，选择性地蚀刻多晶硅膜（3）。 使用作为保护膜的沟槽（7）中的绝缘膜（30）可防止基板（1）被蚀刻，从而防止沟槽（7）的形状发生变化。 这导致防止在光刻工艺期间对准精度降低。
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公开(公告)号：US20070204681A1
公开(公告)日：2007-09-06
申请号：US11710974
申请日：2007-02-27
CPC分类号： G01Q70/12 , C12N15/89 , G01Q60/54 , Y10S977/86 , Y10S977/863 , Y10S977/875 , Y10S977/876 , Y10S977/879
摘要： A carbon thin line probe having a carbon thin line selectively formed at a projection-like terminal end portion thereof by means of an irradiation of high-energy beam, the carbon thin line internally containing a metal. Thereby achieved is a carbon thin line probe suitable for example for the probe of SPM cantilever, which has a high aspect ratio and high durability and reliability, capability of batch processing based on a simple manufacturing method, and to which magnetic characteristic can be imparted.
摘要翻译： 一种碳细线探针，其具有通过高能束的照射在其突起状端部选择性地形成的碳细线，所述碳细线在内部含有金属。 由此实现了适用于例如SPM悬臂的探针的碳细线探针，其具有高纵横比和高耐久性和可靠性，基于简单制造方法的批处理能力，并且可赋予其磁特性。
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公开(公告)号：US20080121029A1
公开(公告)日：2008-05-29
申请号：US12007615
申请日：2008-01-14
申请人： Masashi Kitazawa , Junpei Yoneyama
发明人： Masashi Kitazawa , Junpei Yoneyama
IPC分类号： G01N13/16
摘要： A cantilever having a support portion, a lever portion extended from the support portion, and a probe portion formed in the vicinity of a free end of the lever portion, in which a carbon nano-tube controlled in direction is attached to the probe portion in a manner jutting out from a terminal end portion of the probe portion.
摘要翻译： 具有支撑部的悬臂，从所述支撑部延伸的杆部，以及形成在所述杆部的自由端附近的探针部，所述探针部在所述杆部的自由端附近以将所述方向控制的碳纳米管附接到所述探针部的方式 从探针部的末端部突出的方式。
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公开(公告)号：US07010966B2
公开(公告)日：2006-03-14
申请号：US10694358
申请日：2003-10-28
申请人： Masashi Kitazawa , Koichi Shiotani , Akitoshi Toda
发明人： Masashi Kitazawa , Koichi Shiotani , Akitoshi Toda
IPC分类号： G01B5/28
摘要： Disclosed herein is SPM cantilever having a support portion, a lever portion extended from the support portion and a probe portion formed at a free end of the lever portion, said probe portion having a generally plate-like form and the probe portion having an additionally sharpened terminal end portion. The terminal end portion has its length greater than the plate thickness thereof and is reduced in thickness toward a tip of the terminal end portion, and the tip is located inwardly of the planes extended from the front and back sides of a base portion of the plate-like probe portion.
摘要翻译： 本文公开了具有支撑部分的SPM悬臂，从支撑部分延伸的杆部分和形成在杠杆部分的自由端的探针部分，所述探针部分具有大致板形的形状，并且探针部分具有另外锋利的 末端部。 终端部的长度大于其板厚，并且朝向终端部的前端减小，并且该端部位于从板的基部的前后侧延伸的平面的内侧 样的探针部分。
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公开(公告)号：US20050160802A1
公开(公告)日：2005-07-28
申请号：US11080438
申请日：2005-03-16
申请人： Masashi Kitazawa , Koichi Shiotani , Akitoshi Toda
发明人： Masashi Kitazawa , Koichi Shiotani , Akitoshi Toda
IPC分类号： G01Q30/08 , G01Q30/10 , G01Q30/20 , G01Q60/38 , G01Q70/10 , G01Q70/14 , G01Q70/16 , H01L27/14 , G12B21/02
摘要： Disclosed herein is SPM cantilever having a support portion, a lever portion extended from the support portion and a probe portion formed at a free end of the lever portion, said probe portion having a generally plate-like form and the probe portion having an additionally sharpened terminal end portion. The terminal end portion has its length greater than the plate thickness thereof and is reduced in thickness toward a tip of the terminal end portion, and the tip is located inwardly of the planes extended from the front and back sides of a base portion of the plate-like probe portion.
摘要翻译： 本文公开了具有支撑部分的SPM悬臂，从支撑部分延伸的杆部分和形成在杠杆部分的自由端的探针部分，所述探针部分具有大致板形的形状，并且探针部分具有另外锋利的 末端部。 终端部的长度大于其板厚，并且朝向终端部的前端减小，并且该端部位于从板的基部的前后侧延伸的平面的内侧 样的探针部分。
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公开(公告)号：US06525380B2
公开(公告)日：2003-02-25
申请号：US09324805
申请日：1999-06-03
IPC分类号： H01L2994
CPC分类号： H01L27/092 , H01L21/28176 , H01L21/823857
摘要： A semiconductor device—which includes surface-type n-channel and p-channel single gate transistors by formation of fixed charges within a gate oxide film—and a manufacturing method therefor. A voltage is applied between an electrode connected to a gate electrode and an electrode connected to an N+ region formed in an n-well, and electrons are implanted into the gate electrode at high energy from a substrate, thereby producing fixed negative electric charges in a gate oxide film within an range of 1E11 cm−2 to 1E14 cm−2. An appropriate value for Vth is obtained in the surface channel MOSFET. Therefore, there are solved problems associated with a dual gate structure; namely, a complicated process flow, etch residues or excessive etching due to a difference in etch rate between n-type polycrystalline silicon and p-type polycrystalline silicon, and the deterioration of a gate oxide film due to penetration of boron ions.
摘要翻译： 一种半导体器件及其制造方法，其包括在栅极氧化膜内形成固定电荷的表面型n沟道和p沟道单栅极晶体管。 在连接到栅电极的电极和连接到形成在n阱中的N +区域的电极之间施加电压，并且电子以高能量从衬底注入到栅电极中，从而在电极中产生固定的负电荷 栅极氧化膜在1E11cm-2至1E14cm-2的范围内。 在表面沟道MOSFET中获得适当的Vth值。 因此，解决了与双栅结构相关的问题; 即由于n型多晶硅和p型多晶硅之间的蚀刻速率差异导致的复杂工艺流程，蚀刻残留物或过度蚀刻以及由于硼离子渗透导致的栅极氧化膜的劣化。
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公开(公告)号：US07735357B2
公开(公告)日：2010-06-15
申请号：US11587207
申请日：2005-04-20
申请人： Masashi Kitazawa , Ryo Ota , Masaki Tanemura
发明人： Masashi Kitazawa , Ryo Ota , Masaki Tanemura
IPC分类号： G01B5/28
CPC分类号： G01Q70/12 , Y10S977/849 , Y10S977/86
摘要： An SPM cantilever of the present invention including: a support portion (1) fabricated by processing a single crystal silicon wafer; a lever portion (2) formed in a manner extended from the support portion; a probe (3) disposed at a free end side of the lever portion; a coating of graphite film (5) covering all over the side on which the probe is formed and the entire probe; and a piece of thin line (6) consisting of a carbon nanofiber (CNF) or carbon nanotube (CNT) or graphite nanofiber (GNF) grown/formed from the graphite film at a probe terminal end portion (3a).
摘要翻译： 本发明的SPM悬臂包括：通过处理单晶硅晶片制造的支撑部分（1）; 以从所述支撑部延伸的方式形成的杆部（2） 设置在所述杆部的自由端侧的探针（3） 覆盖在其上形成探针的一侧的整个探针的石墨膜（5）涂层; 以及由在探针末端部分（3a）由石墨膜生长/形成的碳纳米纤维（CNF）或碳纳米管（CNT）或石墨纳米纤维（GNF）组成的细线（6）。
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