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公开(公告)号：US20110140277A1
公开(公告)日：2011-06-16
申请号：US13030861
申请日：2011-02-18
申请人： Takashi OKUDA , Yasuo Morimoto , Yuko Maruyama , Toshio Kumamoto
发明人： Takashi OKUDA , Yasuo Morimoto , Yuko Maruyama , Toshio Kumamoto
IPC分类号： H01L23/522
CPC分类号： H01L23/5223 , H01L23/5225 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.
摘要翻译： 半导体器件包括：包括主表面的半导体衬底; 多个第一互连形成在形成在主表面上并沿预定方向延伸的电容形成区域中; 多个第二互连，每个相邻于位于电容形成区域的边缘处的第一互连，沿预定方向延伸并具有固定电位; 以及绝缘层，形成在主表面上，并且填充在每个第一互连之间以及第一互连和第二互连之间相邻。 第一互连和第二互连在平行于主表面的平面中以基本相等的间隔定位，并且被定位成在基本上垂直于预定方向的方向上对齐。
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公开(公告)号：US20090267816A1
公开(公告)日：2009-10-29
申请号：US12411142
申请日：2009-03-25
IPC分类号： H03M1/20
摘要： There is provided a technique for reducing the adverse effect of idle tones in the channels in a ΔΣ-type A/D converter including a plurality of channels for converting analog input signals into digital signals. The ΔΣ-type A/D converter includes an L channel for converting a left analog input signal into a digital signal and an R channel for converting a right analog input signal into a digital signal. Each of the L channel and the R channel includes a DC dither circuit for generating a DC addition voltage for shifting the frequency of an idle tone. In the L channel and the R channel, DC addition voltages generated by DC dither circuits are different from each other.
摘要翻译： 提供了一种降低ΔSigma型A / D转换器中的通道中的空闲音调的不利影响的技术，其包括用于将模拟输入信号转换为数字信号的多个通道。 DeltaSigma型A / D转换器包括用于将左模拟输入信号转换为数字信号的L通道和用于将右模拟输入信号转换为数字信号的R通道。 L沟道和R沟道中的每一个包括用于产生用于移动空闲频率的频率的DC附加电压的DC抖动电路。 在L沟道和R沟道中，由DC抖动电路产生的直流相加电压彼此不同。
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公开(公告)号：US20090250788A1
公开(公告)日：2009-10-08
申请号：US12485528
申请日：2009-06-16
申请人： Takashi OKUDA , Yasuo Morimoto , Yuko Maruyama , Toshio Kumamoto
发明人： Takashi OKUDA , Yasuo Morimoto , Yuko Maruyama , Toshio Kumamoto
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L23/5225 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction, a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.
摘要翻译： 半导体器件包括：包括主表面的半导体衬底; 形成在主表面上并沿预定方向延伸的电容形成区域中的多个第一互连，多个第二互连，每个第二互连相邻于位于电容形成区域边缘的第一互连件，沿预定方向延伸; 并具有固定的潜力; 以及绝缘层，形成在主表面上，并且填充在每个第一互连之间以及第一互连和第二互连之间相邻。 第一互连和第二互连在平行于主表面的平面中以基本相等的间隔定位，并且被定位成在基本上垂直于预定方向的方向上对齐。
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公开(公告)号：US20090127713A1
公开(公告)日：2009-05-21
申请号：US12267166
申请日：2008-11-07
申请人： Takashi OKUDA , Toshio KUMAMOTO
发明人： Takashi OKUDA , Toshio KUMAMOTO
IPC分类号： H01L23/48
CPC分类号： H01L23/585 , H01L27/0248 , H01L27/092 , H01L2924/0002 , H01L2924/00
摘要： It is an object of the present invention to surely protect a predetermined semiconductor element or a predetermined semiconductor element group in an analog block from a noise generated from a digital block. A semiconductor device according to the present invention includes a semiconductor substrate, a digital block to be a region in which a digital circuit is formed and an analog block to be a region in which an analog circuit is formed, arranged by separating an upper surface of the semiconductor substrate and a substrate potential fixing region provided on the semiconductor substrate so as to surround in a planar view the predetermined semiconductor element group in the analog block, and a pad connected to the substrate potential fixing region and receiving a predetermined potential from an external part.
摘要翻译： 本发明的目的是确保将模拟块中的预定半导体元件或预定半导体元件组与数字块产生的噪声保护起来。 根据本发明的半导体器件包括半导体衬底，作为形成数字电路的区域的数字块和形成模拟电路的区域的模拟块，通过将模拟电路的上表面 半导体基板和设置在半导体基板上的基板电位固定区域，以在平面图中包围模拟块中的预定半导体元件组，以及连接到基板电位固定区域并从外部接收预定电位的焊盘 部分。
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公开(公告)号：US20080001255A1
公开(公告)日：2008-01-03
申请号：US11845348
申请日：2007-08-27
申请人： Takashi OKUDA , Yasuo Morimoto , Yuko Maruyama , Toshio Kumamoto
发明人： Takashi OKUDA , Yasuo Morimoto , Yuko Maruyama , Toshio Kumamoto
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L23/5225 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.
摘要翻译： 半导体器件包括：包括主表面的半导体衬底; 多个第一互连形成在形成在主表面上并沿预定方向延伸的电容形成区域中; 多个第二互连，每个相邻于位于电容形成区域的边缘处的第一互连，沿预定方向延伸并具有固定电位; 以及绝缘层，形成在主表面上，并且填充在每个第一互连之间以及第一互连和第二互连之间相邻。 第一互连和第二互连在平行于主表面的平面中以基本相等的间隔定位，并且被定位成在基本上垂直于预定方向的方向上对齐。
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公开(公告)号：US20130057419A1
公开(公告)日：2013-03-07
申请号：US13523592
申请日：2012-06-14
IPC分类号： H03M3/02
摘要： A delta-sigma A/D converter having plural input channels comprises a first quantizer which quantizes and outputs a received signal; a first D/A converter which converts an output signal of the first quantizer into an analog signal, and outputs the converted analog signal; a first operation unit which outputs a signal indicative of a difference of the first analog input signal and an output signal of the first D/A converter; a first integrator which integrates an output signal of the first operation unit and outputs the integrated signal; a first dither circuit which generates a first dither signal; and a second operation unit which adds the first dither signal to the output signal of the first integrator and outputs the added signal to the first quantizer.
摘要翻译： 具有多个输入通道的Δ-ΣA / D转换器包括量化并输出接收信号的第一量化器; 第一D / A转换器，其将第一量化器的输出信号转换为模拟信号，并输出转换的模拟信号; 第一操作单元，其输出表示第一模拟输入信号和第一D / A转换器的输出信号的差的信号; 第一积分器，其对第一运算单元的输出信号进行积分并输出积分信号; 产生第一抖动信号的第一抖动电路; 以及第二操作单元，其将第一抖动信号添加到第一积分器的输出信号，并将相加的信号输出到第一量化器。
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公开(公告)号：US20070296059A1
公开(公告)日：2007-12-27
申请号：US11845339
申请日：2007-08-27
申请人： Takashi OKUDA , Yasuo Morimoto , Yuko Maruyama , Toshio Kumamoto
发明人： Takashi OKUDA , Yasuo Morimoto , Yuko Maruyama , Toshio Kumamoto
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L23/5225 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.
摘要翻译： 半导体器件包括：包括主表面的半导体衬底; 多个第一互连形成在形成在主表面上并沿预定方向延伸的电容形成区域中; 多个第二互连，每个相邻于位于电容形成区域的边缘处的第一互连，沿预定方向延伸并具有固定电位; 以及绝缘层，形成在主表面上，并且填充在每个第一互连之间以及第一互连和第二互连之间相邻。 第一互连和第二互连在平行于主表面的平面中以基本相等的间隔定位，并且被定位成在基本上垂直于预定方向的方向上对齐。
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